b a x b a y 0 0 0 0 1 0 0 1 0 0 1 0 0 0 2 0 1 0 1 0 1 3 0 1 1 0 1 1 4 1 0 0 0 0 0 5 1 0 1 1 1 0 6 1 1 0 0 0 0 7 1 1 1 1 1 0 b a x b 0 0 0 0 1 1 0 0 1 0 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1 b a x a 0 0 0 0 0 1 0 0 1 0 2 0 1 0 0 3 0 1 1 1 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1 b a x y 0 0 0 0 0 1 0 0 1 0 2 0 1 0 1 3 0 1 1 1 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 0 b a x b 0 0 0 0 1 2 0 1 0 1 5 1 0 1 1 7 1 1 1 1 b a x a 3 0 1 1 1 5 1 0 1 1 7 1 1 1 1 b a x y 2 0 1 0 1 3 0 1 1 1 b a x b Gruppe 0: 0 0 0 0 1 Gruppe 1: 2 0 1 0 1 Gruppe 2: 5 1 0 1 1 Gruppe 3: 7 1 1 1 1 0:2 0 - 0 5:7 1 - 1 b <= (not b and not x) or (b and x) b a x a Gruppe 2: 3 0 1 1 1 5 1 0 1 1 Gruppe 3: 7 1 1 1 1 3:7 - 1 1 5:7 1 - 1 a <= (a and x) or (b and x) b a x y 2 0 1 0 1 3 0 1 1 1 2:3 0 1 - b <= (not b and not x) or (b and x) a <= (a and x) or (b and x) y <= (not b and a)
entity meinausgangsschaltnetz is port ( b, a: inout bit; x: in bit ); end; entity meinuebergangsschaltnetz is port ( b, a: in bit; y: out bit ); end; architecture verhalten of meinausgangsschaltnetz is begin b <= (not b and not x) or (b and x) a <= (a and x) or (b and x) end; architecture verhalten of meinuebergangsschaltnetz is begin y <= (not b and a) end;