0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 1 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 1 10 1 0 1 0 0 11 1 0 1 1 1 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 0 0 0 0 0 1 2 0 0 1 0 1 9 1 0 0 1 1 11 1 0 1 1 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 Gruppe 0: 0 0 0 0 0 1 Gruppe 1: 2 0 0 1 0 1 Gruppe 2: 9 1 0 0 1 1 Gruppe 3: 11 1 0 1 1 1 13 1 1 0 1 1 14 1 1 1 0 1 Gruppe 4: 15 1 1 1 1 1 0:2 0 0 - 0 9:11 1 0 - 1 9:13 1 - 0 1 11:15 1 - 1 1 13:15 1 1 - 1 14:15 1 1 1 - 0:2 0 0 - 0 9:11 1 0 - 1 13:15 1 1 - 1 9:13 1 - 0 1 11:15 1 - 1 1 14:15 1 1 1 - Gruppe 0: 0:2 0 0 - 0 Gruppe 2: 9:11 1 0 - 1 Gruppe 3: 13:15 1 1 - 1 0:2 0 0 - 0 9:11:13:15 1 - - 1 Gruppe 2: 9:13 1 - 0 1 Gruppe 3: 11:15 1 - 1 1 9:13:11:15 1 - - 1 14:15 1 1 1 - 0:2 0 0 - 0 9:11:13:15 1 - - 1 9:13:11:15 1 - - 1 14:15 1 1 1 - 0:2 0 0 - 0 9:11:13:15 1 - - 1 14:15 1 1 1 - 0 2 9 11 13 14 15 0:2 * * 9:11:13:15 * * * * 14:15 * * y <= (not x3 and not x2 and not x0) or (x3 and not x0) or (x3 and x2 and x1)
entity meinschaltnetz is port ( x3, x2, x1, x0: in bit; y: out bit ); end; architecture verhalten of meinschaltnetz begin y <= (not x3 and not x2 and not x0) or (x3 and not x0) or (x3 and x2 and x1) end;