A B C D [CODE] 0 00 0 2 [CODE] 0 01 0 2 [CODE] 1 00 1 3 [CODE] 2 00 0 2 [CODE] 3 00 1 2 [CODE] 3 01 1 1 [CODE] A: Aktueller Zustand B: Eingabe, x1, x2 C: Ausgabe, y, D: Folgezustand A B C D Code Folgezustand 0 00 0 2 0100 0 01 0 2 0100 1 00 1 3 1000 2 00 0 2 0100 3 00 1 2 0100 3 01 1 1 0010 A: Aktueller Zustand B: Eingabe, x1, x2 C: Ausgabe, y, D: Folgezustand z1+ := z3 AND (NOT x1 AND x0) z2+ := z0 AND (NOT x1 AND NOT x0) OR (z0 AND NOT x1 AND x0) OR (z2 AND NOT x1 AND NOT x0) OR (z3 AND NOT x1 AND NOT x0) z3+ := z1 AND (NOT x1 AND NOT x0) y := (z1 AND NOT x1 AND NOT x0) OR (z3 AND NOT x1 AND NOT x0) OR (z3 AND NOT x1 AND x0) z1s <= z3 and (not x1 and x0); z2s <= z0 and (not x1 and not x0) or (z0 and not x1 and x0) or (z2 and not x1 and not x0) or (z3 and not x1 and not x0); z3s <= z1 and (not x1 and not x0); y <= (z1 and not x1 and not x0) or (z3 and not x1 and not x0) or (z3 and not x1 and x0); library ieee; use ieee.std_logic_1164.all; entity automat20240106 is port ( z3s, z2s, z1s, z0s: out std_logic; y: out std_logic; z3, z2, z1, z0: in std_logic; x1, x0: in std_logic ); end; architecture behaviour of automat20240106 is begin z1s <= z3 and (not x1 and x0); z2s <= (z0 and (not x1 and not x0)) or (z0 and not x1 and x0) or (z2 and not x1 and not x0) or (z3 and not x1 and not x0); z3s <= z1 and (not x1 and not x0); y <= (z1 and not x1 and not x0) or (z3 and not x1 and not x0) or (z3 and not x1 and x0); end; library ieee; use ieee.std_logic_1164.all; entity automat20240106testbench is port ( z3s, z2s, z1s, z0s: out std_logic; y: out std_logic ); end; architecture behaviour of automat20240106testbench is component automat20240106 port ( z3s, z2s, z1s, z0s: out std_logic; y: out std_logic; z3, z2, z1, z0: in std_logic; x1, x0: in std_logic ); end component; signal z3, z2, z1, z0: std_logic; signal x1, x0: std_logic; begin sn: automat20240106 PORT MAP (z3s=>z3s, z2s=>z2s, z1s=>z1s, z0s=>z0s, y=>y, z3=>z3, z2=>z2, z1=>z1, z0=>z0, x1=>x1, x0=>x0); z0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns; z1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns; z2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; z3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; x0 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; x1 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; end;

library ieee; use ieee.std_logic_1164.all; entity automat20240106 is port ( z3s, z2s, z1s, z0s: out std_logic; y: out std_logic; z3, z2, z1, z0: in std_logic; x1, x0: in std_logic ); end; architecture behaviour of automat20240106 is begin z1s <= z3 and (not x1 and x0); z2s <= (z0 and (not x1 and not x0)) or (z0 and not x1 and x0) or (z2 and not x1 and not x0) or (z3 and not x1 and not x0); z3s <= z1 and (not x1 and not x0); y <= (z1 and not x1 and not x0) or (z3 and not x1 and not x0) or (z3 and not x1 and x0); end; library ieee; use ieee.std_logic_1164.all; entity automat20240106testbench is port ( z3s, z2s, z1s, z0s: out std_logic; y: out std_logic ); end; architecture behaviour of automat20240106testbench is component automat20240106 port ( z3s, z2s, z1s, z0s: out std_logic; y: out std_logic; z3, z2, z1, z0: in std_logic; x1, x0: in std_logic ); end component; signal z3, z2, z1, z0: std_logic; signal x1, x0: std_logic; begin sn: automat20240106 PORT MAP (z3s=>z3s, z2s=>z2s, z1s=>z1s, z0s=>z0s, y=>y, z3=>z3, z2=>z2, z1=>z1, z0=>z0, x1=>x1, x0=>x0); z0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns; z1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns; z2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; z3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; x0 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; x1 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; end;