Nächste Seite: in VHDL Aufwärts: 2024-11-28 Vorherige Seite: TTL-Gatter und Disjunktive Normalform
(C) David Vajda
Quine Mc Cluskey VHDL - Disjunktive/Konjunktive Normalform
2024-11-18
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
0 0 0 0 0 1
2 0 0 1 0 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
12 1 1 0 0 1
13 1 1 0 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
12 1 1 0 0 1
Gruppe 3:
13 1 1 0 1 1
0:2 0 0 - 0
0:4 0 - 0 0
2:6 0 - 1 0
4:5 0 1 0 -
4:6 0 1 - 0
4:12 - 1 0 0
5:13 - 1 0 1
12:13 1 1 0 -
4:5 0 1 0 -
12:13 1 1 0 -
0:2 0 0 - 0
4:6 0 1 - 0
0:4 0 - 0 0
2:6 0 - 1 0
4:12 - 1 0 0
5:13 - 1 0 1
4:5 0 1 0 -
12:13 1 1 0 -
4:5:12:13 - 1 0 -
0:2 0 0 - 0
4:6 0 1 - 0
0:2:4:6 0 - - 0
0:4 0 - 0 0
2:6 0 - 1 0
0:4:2:6 0 - - 0
4:12 - 1 0 0
5:13 - 1 0 1
4:12:5:13 - 1 0 -
4:5:12:13 - 1 0 -
0:2:4:6 0 - - 0
0:4:2:6 0 - - 0
4:12:5:13 - 1 0 -
4:5:12:13 - 1 0 -
0:2:4:6 0 - - 0
DNF:
y <= (x2 and not x1) or
(not x3 and not x0);
=== KNF:
y <= not (
(not x2 or x1) and
(x3 or x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20241128 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241128 is
begin
y <= not (
(not x2 or x1) and
(x3 or x0)
);
end;
library ieee;
use ieee.std_logic_1164;
entity quine20241128testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241128testbench is
component quine20241128
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241128 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
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