(C) David Vajda 2024-11-30 Quine Mc Cluskey, DNF, KNF 0 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 0 12 1 1 0 0 0 13 1 1 0 1 0 14 1 1 1 0 0 15 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 Gruppe 0: 0 0 0 0 0 1 Gruppe 1: 1 0 0 0 1 1 2 0 0 1 0 1 4 0 1 0 0 1 8 1 0 0 0 1 Gruppe 2: 3 0 0 1 1 1 9 1 0 0 1 1 10 1 0 1 0 1 0:1 0 0 0 - 0:2 0 0 - 0 0:4 0 - 0 0 0:8 - 0 0 0 1:3 0 0 - 1 1:9 - 0 0 1 2:3 0 0 1 - 2:10 - 0 1 0 8:9 1 0 0 - 8:10 1 0 - 0 1:9 - 0 0 1 2:10 - 0 1 0 0:8 - 0 0 0 0:4 0 - 0 0 0:2 0 0 - 0 1:3 0 0 - 1 8:10 1 0 - 0 0:1 0 0 0 - 2:3 0 0 1 - 8:9 1 0 0 - 1:9 - 0 0 1 2:10 - 0 1 0 0:8 - 0 0 0 0:8:1:9 - 0 0 - 0:8:2:10 - 0 - 0 0:4 0 - 0 0 0:4 0 - 0 0 0:2 0 0 - 0 1:3 0 0 - 1 8:10 1 0 - 0 0:2:1:3 0 0 - - 0:2:8:10 - 0 - 0 0:1 0 0 0 - 2:3 0 0 1 - 8:9 1 0 0 - 0:1:2:3 0 0 - - 0:1:8:9 - 0 0 - 0:8:1:9 - 0 0 - 0:8:2:10 - 0 - 0 0:4 0 - 0 0 0:2:1:3 0 0 - - 0:2:8:10 - 0 - 0 0:1:2:3 0 0 - - 0:1:8:9 - 0 0 - 0:8:1:9 - 0 0 - 0:1:8:9 - 0 0 - 0:8:2:10 - 0 - 0 0:2:8:10 - 0 - 0 0:4 0 - 0 0 0:2:1:3 0 0 - - 0:1:2:3 0 0 - - 0:8:1:9 - 0 0 - 0:8:2:10 - 0 - 0 0:4 0 - 0 0 0:2:1:3 0 0 - - 0 1 2 3 4 8 9 10 0:8:1:9 + + + + 0:8:2:10 + + + + 0:4 + + 0:2:1:3 + + + + 0:8:1:9 - 0 0 - 0:8:2:10 - 0 - 0 0:4 0 - 0 0 0:2:1:3 0 0 - - y <= (not x2 and not x1) or (not x2 and not x0) or (not x3 and not x1 and not x0) or (not x3 and not x2); y <= not ( (x2 or x1) and (x2 or x0) and (x3 or x1 or x0) and (x3 or x2) ); library ieee; use ieee.std_logic_1164.all; entity quine20241130 is port ( x3, x2, x1, x0: in std_logic; y: out std_logic ); end; architecture behaviour of quine20241130 is begin y <= (not x2 and not x1) or (not x2 and not x0) or (not x3 and not x1 and not x0) or (not x3 and not x2); end; library ieee; use ieee.std_logic_1164.all; entity quine20241130testbench is port ( y: out std_logic ); end; architecture behaviour of quine20241130testbench is component quine20241130 port ( x3, x2, x1, x0: in std_logic; y: out std_logic ); end component; signal x3, x2, x1, x0: std_logic; begin q: quine20241130 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y); |