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32 Bit Ripple Carry Chain Addierer
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32testbench is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
-- 19219 + 14823 = 34042
-- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
s <= '0';
end;
|
Subtrahierer:
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32testbench is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
-- 19219 + 14823 = 34042
-- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity com32 is
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of com32 is
begin
com_connect: FOR i IN 31 DOWNTO 0 GENERATE
y (i) <= not x (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity neg32 is
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of neg32 is
component com32
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end component;
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal d: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
d (i) <= '0';
END GENERATE;
s <= '1';
com: com32 PORT MAP (x=>a, y=>c);
add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32 is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component neg32
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal x: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg: neg32 PORT MAP (a=>a, b=>x);
add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32testbench is
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
s <= '0' after 0 ns, '1' after 10 ns;
-- 19219 - 14823 =
end;
|
19219 - 14823 = 4396 === 0x112C 14823 - 19219 = -4396 === 0xFFFFFFFFFFFFEED4 |
-- (C) David Vajda
-- 32 Bit x 2:1 MUX
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity DeMUX32_2_1 is
port (
c: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0);
a: out std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of DeMUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
a (i) <= (c (i) and not x);
b (i) <= (c (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity DeMUX32_2_1testbench is
port (
a: out std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of DeMUX32_2_1testbench is
component DeMUX32_2_1 is
port (
c: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0);
a: out std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: DeMUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
c <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
|
jetzt kommen 5 kaskadierte MUX
-- (C) David Vajda
-- 32 Bit x 2:1 MUX
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
package MIPS32 is
type bus2_32 is array (1 downto 0) of std_logic_vector (31 downto 0);
type bus4_32 is array (1 downto 0) of std_logic_vector (31 downto 0);
end package;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.mips32.all;
entity MUX32_2_1 is
port (
b: out std_logic_vector (31 downto 0);
a: in bus2_32;
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
b (i) <= (a (1)(i) and not x) or (a(0) (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.mips32.all;
entity MUX32_4_1 is
port (
b: out std_logic_vector (31 downto 0);
a: in bus4_32;
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
component MUX32_2_1
port (
b: out std_logic_vector (31 downto 0);
a: in bus2_32;
x: in std_logic
);
end component;
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
b (i) <= (a (1)(i) and not x) or (a(0) (i) and x);
END GENERATE;
end;
|
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
|
so weit so gut
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
|
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and regdest;
c2 <= en and not regdest;
end;
|
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and regdest;
c2 <= en and not regdest;
end;
|
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset2_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset2_32testbench is
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic;
signal regsrc2: std_logic;
signal regdest: std_logic;
signal en: std_logic;
begin
regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= '0' after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= '0' after 0 ns;
regsrc1 <= '0' after 0 ns;
regsrc2 <= '0' after 0 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= ('0','0') after 0 ns;
regsrc1 <= ('0','0') after 0 ns;
regsrc2 <= ('0','0') after 0 ns;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
-- ...
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= ('0','0') after 0 ns;
regsrc1 <= ('0','0') after 0 ns;
regsrc2 <= ('0','0') after 0 ns;
end;
|
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset2_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset2_32testbench is
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic;
signal regsrc2: std_logic;
signal regdest: std_logic;
signal en: std_logic;
begin
regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= '0' after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= '0' after 0 ns;
regsrc1 <= '0' after 0 ns;
regsrc2 <= '0' after 0 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
-- regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
|
signal dword32: std_logic_vector (31 downto 0); signal word16low: std_logic_vector (15 downto 0); signal word16high: std_logic_vector (15 downto 0); word16low <= dword32 (15 downto 0); |
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset2_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset2_32testbench is
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic;
signal regsrc2: std_logic;
signal regdest: std_logic;
signal en: std_logic;
begin
regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= '0' after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= '0' after 0 ns;
regsrc1 <= '0' after 0 ns;
regsrc2 <= '0' after 0 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
-- regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
|
Hier noch mal
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset2_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset2_32testbench is
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic;
signal regsrc2: std_logic;
signal regdest: std_logic;
signal en: std_logic;
begin
regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= '0' after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= '0' after 0 ns;
regsrc1 <= '0' after 0 ns;
regsrc2 <= '0' after 0 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
-- regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
|
-- jetzt kann man das so machen
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
null: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
);
end component;
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) and a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
null: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end component;
begin
end;
|
Und noch weiter
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) and a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
null: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd);
mux2: MUX32_2_1 PORT MAP ();
mux3: MUX32_2_1 PORT MAP ();
add1: add1 PORT MAP (a=>a, b=>b, s=>sadd, t=>globaltflag, c=>cadd);
sub1: sub1 PORT MAP (a=>a, b=>b, t=>globaltflag, c=>csub);
and1: and1 PORT MAP (a=>a, b=>b, c=>cand);
or1: or1 PORT MAP (a=>a, b=>b, c=>cor);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: out std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z4, z3, z2, z1: std_logic;
signal x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>c, x=>x3);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
z1 <= (not s (2) and s (1) and not s (0));
z2 <= (s(2) and s(1) and not s(0));
z3 <= (not s (2) and not s (1) and not s (0));
z4 <= (not s (2) and not s (1) and s (0));
--
-- z4 z3 z2 z1 x3 x2 x1
-- 0 0 0 1 0 x 0
-- 0 0 1 0 0 x 1
-- 0 1 0 0 1 1 x
-- 1 0 0 0 1 0 x
-- x3 <= z3 or z4
-- x2 <= z3
-- x1 <= z2
x3 <= z3 or z4;
x2 <= z3;
x1 <= z2;
sadd <= '0';
end;
|
-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset2_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset2_32testbench is
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic;
signal regsrc2: std_logic;
signal regdest: std_logic;
signal en: std_logic;
begin
regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= '0' after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= '0' after 0 ns;
regsrc1 <= '0' after 0 ns;
regsrc2 <= '0' after 0 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
-- regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
|
-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX5_2_1 is
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX5_2_1 is
begin
MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset2_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset2_32testbench is
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic;
signal regsrc2: std_logic;
signal regdest: std_logic;
signal en: std_logic;
begin
regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= '0' after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= '0' after 0 ns;
regsrc1 <= '0' after 0 ns;
regsrc2 <= '0' after 0 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
-- regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32testbench is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
-- 19219 + 14823 = 34042
-- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity com32 is
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of com32 is
begin
com_connect: FOR i IN 31 DOWNTO 0 GENERATE
y (i) <= not x (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity neg32 is
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of neg32 is
component com32
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end component;
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal d: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
d (i) <= '0';
END GENERATE;
s <= '1';
com: com32 PORT MAP (x=>a, y=>c);
add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32 is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component neg32
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal x: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg: neg32 PORT MAP (a=>a, b=>x);
add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32testbench is
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
s <= '0' after 0 ns, '1' after 10 ns;
-- 19219 - 14823 =
end;
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) and a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram is
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of sram is
begin
readdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of prom is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z4, z3, z2, z1: std_logic;
signal x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
z1 <= (not s (2) and s (1) and not s (0));
z2 <= (s(2) and s(1) and not s(0));
z3 <= (not s (2) and not s (1) and not s (0));
z4 <= (not s (2) and not s (1) and s (0));
--
-- z4 z3 z2 z1 x3 x2 x1
-- 0 0 0 1 0 x 0
-- 0 0 1 0 0 x 1
-- 0 1 0 0 1 1 x
-- 1 0 0 0 1 0 x
-- x3 <= z3 or z4
-- x2 <= z3
-- x1 <= z2
x3 <= z3 or z4;
x2 <= z3;
x1 <= z2;
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity Bit2Shift is
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of Bit2Shift is
begin
b <= a;
end;
library ieee;
use ieee.std_logic_1164.all;
entity signunit is
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of signunit is
begin
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity mips32 is
port (
globalCPUCLK: in std_logic
);
end;
architecture behaviour of mips32 is
component registerset32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end component;
component ALU
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end component;
-- 4 x MUX
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component MUX5_2_1
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end component;
-- befehlszaehler, addierer + 4 u Sprung 2x Addierer
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component Bit2Shift
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component signunit
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component sram
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component prom
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
component opdecode
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end component;
component funcdecode
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end component;
signal op: std_logic_vector (31 downto 0);
signal aluop: std_logic_vector (1 downto 0);
signal func: std_logic_vector (5 downto 0);
signal aluoperation: std_logic_vector (2 downto 0);
signal memtoreg: std_logic;
signal memwrite: std_logic;
signal branch: std_logic;
signal alusrc: std_logic;
signal regdst: std_logic;
signal regwrite: std_logic;
signal pcsrc: std_logic;
signal regdest: std_logic_vector (4 downto 0);
signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
signal signunitBUS: std_logic_vector (31 downto 0);
signal memReadData: std_logic_vector (31 downto 0);
signal destdata: std_logic_vector (31 downto 0);
signal srcdata1: std_logic_vector (31 downto 0);
signal srcdata2: std_logic_vector (31 downto 0);
signal nulbit: std_logic;
signal pcBUSplus: std_logic_vector (31 downto 0);
signal pcBUS: std_logic_vector (31 downto 0);
signal Value32_4: std_logic_vector (31 downto 0);
signal add1cBus: std_logic_vector (31 downto 0);
signal add2cBus: std_logic_vector (31 downto 0);
signal Bit2ShiftBus: std_logic_vector (31 downto 0);
signal Value1_0: std_logic;
signal nullbit: std_logic;
begin
funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite);
mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);
signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);
add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);
pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUCLK);
alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16));
sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData);
prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op);
pcsrc <= nullbit and branch;
Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
Value1_0 <= '0';
op (25 downto 21) <= ('0','0','0','0','0');
op (20 downto 16) <= ('0','0','0','0','0');
regdest <= ('0','0','0','0','0') after 0 ns, ('0','0','0','0','0') after 3 ns;
regwrite <= '0' after 0 ns, '1' after 1 ns, '0' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns;
destdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0') after 0 ns;
end;
|
https://opencores.org/projects/plasma/opcodes
-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p);
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatchtestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dlatchtestbench is
component dlatch
port (
c: in std_logic;
d: in std_logic;
q: inout std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dlatch PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dfftestbench is
port (
q: inout std_logic
);
end;
architecture behaviour of dfftestbench is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal d, c: std_logic;
begin
dl: dff PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dffregtestbench is
port (
q: inout std_logic_vector (31 downto 0)
);
end;
architecture behaviour of dffregtestbench is
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
signal d: std_logic_vector (31 downto 0);
signal c: std_logic;
begin
r32: reg32 PORT MAP (d=>d, c=>c, q=>q);
-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss
d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX5_2_1 is
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX5_2_1 is
begin
MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1testbench is
port (
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of MUX32_2_1testbench is
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal b: std_logic_vector (31 downto 0);
signal a: std_logic_vector (31 downto 0);
signal x: std_logic;
begin
mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);
a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and not regdest;
c2 <= en and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset2_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset2_32testbench is
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic;
signal regsrc2: std_logic;
signal regdest: std_logic;
signal en: std_logic;
begin
regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
regdest <= '0' after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
regdest <= '0' after 0 ns;
regsrc1 <= '0' after 0 ns;
regsrc2 <= '0' after 0 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;
entity registerset4_32testbench is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of registerset4_32testbench is
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal destdata: std_logic_vector (31 downto 0);
signal regsrc1: std_logic_vector (1 downto 0);
signal regsrc2: std_logic_vector (1 downto 0);
signal regdest: std_logic_vector (1 downto 0);
signal en: std_logic;
begin
regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2, regdest=>regdest, en=>en);
-- regdest <= ('0','0') after 0 ns;
destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32testbench is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
-- 19219 + 14823 = 34042
-- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity com32 is
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of com32 is
begin
com_connect: FOR i IN 31 DOWNTO 0 GENERATE
y (i) <= not x (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity neg32 is
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of neg32 is
component com32
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end component;
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal d: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
d (i) <= '0';
END GENERATE;
s <= '1';
com: com32 PORT MAP (x=>a, y=>c);
add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32 is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component neg32
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal x: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg: neg32 PORT MAP (a=>a, b=>x);
add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32testbench is
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
s <= '0' after 0 ns, '1' after 10 ns;
-- 19219 - 14823 =
end;
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= '0';
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram is
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of sram is
begin
readdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of prom is
begin
readdata <= ('0','0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '1','0','0','1','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z4, z3, z2, z1: std_logic;
signal x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
z1 <= (not s (2) and s (1) and not s (0));
z2 <= (s(2) and s(1) and not s(0));
z3 <= (not s (2) and not s (1) and not s (0));
z4 <= (not s (2) and not s (1) and s (0));
--
-- z4 z3 z2 z1 x3 x2 x1
-- 0 0 0 1 0 x 0
-- 0 0 1 0 0 x 1
-- 0 1 0 0 1 0 x
-- 1 0 0 0 1 1 x
-- x3 <= z3 or z4
-- x2 <= z3
-- x1 <= z2
x3 <= z3 or z4;
x2 <= z4;
x1 <= z2;
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0);
cpuclock: in std_logic
);
end;
architecture behaviour of opdecode is
begin
memtoreg <= '0';
memwrite <= '0';
branch <= '0';
alusrc <= '0';
regdst <= '1';
regwrite <= '1' and cpuclock;
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
begin
aluoperation <= ('0', '0', '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity Bit2Shift is
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of Bit2Shift is
begin
b <= a;
end;
library ieee;
use ieee.std_logic_1164.all;
entity signunit is
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of signunit is
begin
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity mips32 is
port (
globalCPUCLK: in std_logic
);
end;
architecture behaviour of mips32 is
component registerset32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic
);
end component;
component ALU
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end component;
-- 4 x MUX
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component MUX5_2_1
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end component;
-- befehlszaehler, addierer + 4 u Sprung 2x Addierer
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component Bit2Shift
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component signunit
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component sram
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component prom
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic
);
end component;
component opdecode
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0);
cpuclock: in std_logic
);
end component;
component funcdecode
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end component;
signal op: std_logic_vector (31 downto 0);
signal aluop: std_logic_vector (1 downto 0);
signal func: std_logic_vector (5 downto 0);
signal aluoperation: std_logic_vector (2 downto 0);
signal memtoreg: std_logic;
signal memwrite: std_logic;
signal branch: std_logic;
signal alusrc: std_logic;
signal regdst: std_logic;
signal regwrite: std_logic;
signal pcsrc: std_logic;
signal regdest: std_logic_vector (4 downto 0);
signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
signal signunitBUS: std_logic_vector (31 downto 0);
signal memReadData: std_logic_vector (31 downto 0);
signal destdata: std_logic_vector (31 downto 0);
signal srcdata1: std_logic_vector (31 downto 0);
signal srcdata2: std_logic_vector (31 downto 0);
signal nulbit: std_logic;
signal pcBUSplus: std_logic_vector (31 downto 0);
signal pcBUS: std_logic_vector (31 downto 0);
signal Value32_4: std_logic_vector (31 downto 0);
signal add1cBus: std_logic_vector (31 downto 0);
signal add2cBus: std_logic_vector (31 downto 0);
signal Bit2ShiftBus: std_logic_vector (31 downto 0);
signal Value1_0: std_logic;
signal nullbit: std_logic;
signal globalCPUC: std_logic;
begin
funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite, cpuclock=>globalCPUC);
mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);
signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);
add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);
pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUC);
alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16));
sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData);
prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op);
pcsrc <= nullbit and branch;
Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
Value1_0 <= '0';
globalCPUC <= '0' after 1 ns, '1' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns;
end;
|
-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p) and not reset;
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q, reset=>reset);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q, reset=>reset);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q, reset=>reset);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e, reset=>reset);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c, reset=>reset);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX5_2_1 is
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX5_2_1 is
begin
MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1, reset=>reset);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2, reset=>reset);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and clk and not regdest;
c2 <= en and clk and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32testbench is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
-- 19219 + 14823 = 34042
-- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity com32 is
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of com32 is
begin
com_connect: FOR i IN 31 DOWNTO 0 GENERATE
y (i) <= not x (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity neg32 is
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of neg32 is
component com32
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end component;
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal d: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
d (i) <= '0';
END GENERATE;
s <= '1';
com: com32 PORT MAP (x=>a, y=>c);
add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32 is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component neg32
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal x: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg: neg32 PORT MAP (a=>a, b=>x);
add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32testbench is
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
s <= '0' after 0 ns, '1' after 10 ns;
-- 19219 - 14823 =
end;
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) and a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram is
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of sram is
begin
readdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of prom is
begin
readdata <= ('0','0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '1','0','0','1','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z4, z3, z2, z1: std_logic;
signal x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
z1 <= (not s (2) and s (1) and not s (0));
z2 <= (s(2) and s(1) and not s(0));
z3 <= (not s (2) and not s (1) and not s (0));
z4 <= (not s (2) and not s (1) and s (0));
--
-- z4 z3 z2 z1 x3 x2 x1
-- 0 0 0 1 0 x 0
-- 0 0 1 0 0 x 1
-- 0 1 0 0 1 0 x
-- 1 0 0 0 1 1 x
-- x3 <= z3 or z4
-- x2 <= z3
-- x1 <= z2
x3 <= z3 or z4;
x2 <= z4;
x1 <= z2;
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0);
cpuclock: in std_logic
);
end;
architecture behaviour of opdecode is
begin
memtoreg <= '0';
memwrite <= '0';
branch <= '0';
alusrc <= '0';
regdst <= '1';
regwrite <= '1' and cpuclock;
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
begin
aluoperation <= ('0', '0', '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity Bit2Shift is
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of Bit2Shift is
begin
b <= a;
end;
library ieee;
use ieee.std_logic_1164.all;
entity signunit is
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of signunit is
begin
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity mips32 is
port (
globalCPUCLK: in std_logic
);
end;
architecture behaviour of mips32 is
component registerset32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
clk: in std_logic;
reset: in std_logic
);
end component;
component ALU
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end component;
-- 4 x MUX
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component MUX5_2_1
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end component;
-- befehlszaehler, addierer + 4 u Sprung 2x Addierer
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component Bit2Shift
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component signunit
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component sram
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component prom
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic;
reset: in std_logic
);
end component;
component opdecode
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0);
cpuclock: in std_logic
);
end component;
component funcdecode
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end component;
signal op: std_logic_vector (31 downto 0);
signal aluop: std_logic_vector (1 downto 0);
signal func: std_logic_vector (5 downto 0);
signal aluoperation: std_logic_vector (2 downto 0);
signal memtoreg: std_logic;
signal memwrite: std_logic;
signal branch: std_logic;
signal alusrc: std_logic;
signal regdst: std_logic;
signal regwrite: std_logic;
signal pcsrc: std_logic;
signal regdest: std_logic_vector (4 downto 0);
signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
signal signunitBUS: std_logic_vector (31 downto 0);
signal memReadData: std_logic_vector (31 downto 0);
signal destdata: std_logic_vector (31 downto 0);
signal srcdata1: std_logic_vector (31 downto 0);
signal srcdata2: std_logic_vector (31 downto 0);
signal nulbit: std_logic;
signal pcBUSplus: std_logic_vector (31 downto 0);
signal pcBUS: std_logic_vector (31 downto 0);
signal Value32_4: std_logic_vector (31 downto 0);
signal add1cBus: std_logic_vector (31 downto 0);
signal add2cBus: std_logic_vector (31 downto 0);
signal Bit2ShiftBus: std_logic_vector (31 downto 0);
signal Value1_0: std_logic;
signal nullbit: std_logic;
signal globalCPUC: std_logic;
signal reset: std_logic;
begin
funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite, cpuclock=>globalCPUC);
mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);
signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);
add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);
pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUC, reset=>reset);
alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16), reset=>reset, clk=>globalCPUC);
sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData);
prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op);
pcsrc <= nullbit and branch;
Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
Value1_0 <= '0';
reset <= '1' after 0 ns, '0' after 2 ns;
globalCPUC <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns, '1' after 6 ns, '0' after 7 ns, '1' after 8 ns, '0' after 9 ns, '1' after 10 ns;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1;
regwrite <= x0 or x1;
end;
|
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1;
regwrite <= x0 or x1;
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
aluop (1) <= x0 or not x1;
aluop (0) <= x0 or not x1;
end;
|
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
begin
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
x1 <= (not aluop (1) and not aluop (0));
aluoperation (2) <= x0;
aluoperation (1) <= x0 or x1;
aluoperation (0) <= x0;
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
end;
|
-- signal x1, x0 vergessen
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x1, x0: std_logic;
begin
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
x1 <= (not aluop (1) and not aluop (0));
aluoperation (2) <= x0;
aluoperation (1) <= x0 or x1;
aluoperation (0) <= x0;
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
end;
|
-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p) and not reset;
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q, reset=>reset);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q, reset=>reset);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q, reset=>reset);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e, reset=>reset);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c, reset=>reset);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX5_2_1 is
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX5_2_1 is
begin
MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1, reset=>reset);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2, reset=>reset);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and clk and not regdest;
c2 <= en and clk and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32testbench is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
-- 19219 + 14823 = 34042
-- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity com32 is
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of com32 is
begin
com_connect: FOR i IN 31 DOWNTO 0 GENERATE
y (i) <= not x (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity neg32 is
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of neg32 is
component com32
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end component;
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal d: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
d (i) <= '0';
END GENERATE;
s <= '1';
com: com32 PORT MAP (x=>a, y=>c);
add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32 is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component neg32
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal x: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg: neg32 PORT MAP (a=>a, b=>x);
add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32testbench is
port (
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32testbench is
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);
a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
s <= '0' after 0 ns, '1' after 10 ns;
-- 19219 - 14823 =
end;
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) and a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram is
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of sram is
begin
readdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of prom is
begin
readdata <= ('0','0','1','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z4, z3, z2, z1: std_logic;
signal x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
z1 <= (not s (2) and s (1) and not s (0));
z2 <= (s(2) and s(1) and not s(0));
z3 <= (not s (2) and not s (1) and not s (0));
z4 <= (not s (2) and not s (1) and s (0));
--
-- z4 z3 z2 z1 x3 x2 x1
-- 0 0 0 1 0 x 0
-- 0 0 1 0 0 x 1
-- 0 1 0 0 1 0 x
-- 1 0 0 0 1 1 x
-- x3 <= z3 or z4
-- x2 <= z3
-- x1 <= z2
x3 <= z3 or z4;
x2 <= z4;
x1 <= z2;
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1;
regwrite <= x0 or x1;
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
aluop (1) <= x0 or not x1;
aluop (0) <= x0 or not x1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x1, x0: std_logic;
begin
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
x1 <= (not aluop (1) and not aluop (0));
aluoperation (2) <= x0;
aluoperation (1) <= x0 or x1;
aluoperation (0) <= x0;
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
end;
library ieee;
use ieee.std_logic_1164.all;
entity Bit2Shift is
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of Bit2Shift is
begin
b (31 downto 2) <= a (29 downto 0);
b (1 downto 0) <= ('0', '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity signunit is
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of signunit is
begin
b (31 downto 16) <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0');
b (15 downto 0) <= a;
end;
library ieee;
use ieee.std_logic_1164.all;
entity mips32 is
port (
globalCPUCLK: in std_logic
);
end;
architecture behaviour of mips32 is
component registerset32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
clk: in std_logic;
reset: in std_logic
);
end component;
component ALU
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end component;
-- 4 x MUX
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component MUX5_2_1
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end component;
-- befehlszaehler, addierer + 4 u Sprung 2x Addierer
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component Bit2Shift
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component signunit
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component sram
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component prom
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end component;
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic;
reset: in std_logic
);
end component;
component opdecode
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end component;
component funcdecode
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end component;
signal op: std_logic_vector (31 downto 0);
signal aluop: std_logic_vector (1 downto 0);
signal func: std_logic_vector (5 downto 0);
signal aluoperation: std_logic_vector (2 downto 0);
signal memtoreg: std_logic;
signal memwrite: std_logic;
signal branch: std_logic;
signal alusrc: std_logic;
signal regdst: std_logic;
signal regwrite: std_logic;
signal pcsrc: std_logic;
signal regdest: std_logic_vector (4 downto 0);
signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
signal signunitBUS: std_logic_vector (31 downto 0);
signal memReadData: std_logic_vector (31 downto 0);
signal destdata: std_logic_vector (31 downto 0);
signal srcdata1: std_logic_vector (31 downto 0);
signal srcdata2: std_logic_vector (31 downto 0);
signal nulbit: std_logic;
signal pcBUSplus: std_logic_vector (31 downto 0);
signal pcBUS: std_logic_vector (31 downto 0);
signal Value32_4: std_logic_vector (31 downto 0);
signal add1cBus: std_logic_vector (31 downto 0);
signal add2cBus: std_logic_vector (31 downto 0);
signal Bit2ShiftBus: std_logic_vector (31 downto 0);
signal Value1_0: std_logic;
signal nullbit: std_logic;
signal globalCPUC: std_logic;
signal reset: std_logic;
begin
funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite);
mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);
signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);
add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);
pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUC, reset=>reset);
alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16), reset=>reset, clk=>globalCPUC);
sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData);
prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op);
pcsrc <= nullbit and branch;
Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
Value1_0 <= '0';
reset <= '1' after 0 ns, '0' after 2 ns;
globalCPUC <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns, '1' after 6 ns, '0' after 7 ns, '1' after 8 ns, '0' after 9 ns, '1' after 10 ns;
end;
|
-- mein programmspeicher liefert uebrigens, das da
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of prom is
begin
readdata <= ('0','0','1','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0');
end;
|
wenn ich das durch
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of prom is
begin
readdata <= ('0','0','1','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','1');
end;
-- ersetze zaehlen wir dreierschritte
|
-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p) and not reset;
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q, reset=>reset);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q, reset=>reset);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q, reset=>reset);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e, reset=>reset);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c, reset=>reset);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX5_2_1 is
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX5_2_1 is
begin
MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1, reset=>reset);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2, reset=>reset);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and clk and not regdest;
c2 <= en and clk and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
----------- SRAM
library ieee;
use ieee.std_logic_1164.all;
entity sram2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1, reset=>reset);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2, reset=>reset);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
c1 <= en and clk and not regdest;
c2 <= en and clk and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
ram1: sram2_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (0), en=>en1, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
ram2: sram2_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (0), en=>en2, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
ram1: sram4_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
ram2: sram4_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
ram1: sram8_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
ram2: sram8_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
ram1: sram16_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
ram2: sram16_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity com32 is
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of com32 is
begin
com_connect: FOR i IN 31 DOWNTO 0 GENERATE
y (i) <= not x (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity neg32 is
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of neg32 is
component com32
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end component;
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal d: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
d (i) <= '0';
END GENERATE;
s <= '1';
com: com32 PORT MAP (x=>a, y=>c);
add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32 is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component neg32
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal x: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg: neg32 PORT MAP (a=>a, b=>x);
add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) and a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram is
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
clk: in std_logic;
reset: in std_logic
);
end;
architecture behaviour of sram is
component sram32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
begin
sram1: sram32_32 PORT MAP (en=>en, clk=>clk, reset=>reset, srcdata1=>readdata, destdata=>writedata, regsrc1=>addrs (4 downto 0), regdest=>addrs (4 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
clk: in std_logic
);
end;
architecture behaviour of prom is
begin
readdata <= ('0','0','1','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z4, z3, z2, z1: std_logic;
signal x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
z1 <= (not s (2) and s (1) and not s (0));
z2 <= (s(2) and s(1) and not s(0));
z3 <= (not s (2) and not s (1) and not s (0));
z4 <= (not s (2) and not s (1) and s (0));
--
-- z4 z3 z2 z1 x3 x2 x1
-- 0 0 0 1 0 x 0
-- 0 0 1 0 0 x 1
-- 0 1 0 0 1 0 x
-- 1 0 0 0 1 1 x
-- x3 <= z3 or z4
-- x2 <= z3
-- x1 <= z2
x3 <= z3 or z4;
x2 <= z4;
x1 <= z2;
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1;
regwrite <= x0 or x1;
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
aluop (1) <= x0 or not x1;
aluop (0) <= x0 or not x1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x1, x0: std_logic;
begin
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
x1 <= (not aluop (1) and not aluop (0));
aluoperation (2) <= x0;
aluoperation (1) <= x0 or x1;
aluoperation (0) <= x0;
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
end;
library ieee;
use ieee.std_logic_1164.all;
entity Bit2Shift is
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of Bit2Shift is
begin
b (31 downto 2) <= a (29 downto 0);
b (1 downto 0) <= ('0', '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity signunit is
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of signunit is
begin
b (31 downto 16) <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0');
b (15 downto 0) <= a;
end;
library ieee;
use ieee.std_logic_1164.all;
entity mips32 is
port (
globalCPUCLK: in std_logic
);
end;
architecture behaviour of mips32 is
component registerset32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
clk: in std_logic;
reset: in std_logic
);
end component;
component ALU
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end component;
-- 4 x MUX
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component MUX5_2_1
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end component;
-- befehlszaehler, addierer + 4 u Sprung 2x Addierer
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component Bit2Shift
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component signunit
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component sram
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
reset: in std_logic;
clk: in std_logic
);
end component;
component prom
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
clk: in std_logic
);
end component;
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic;
reset: in std_logic
);
end component;
component opdecode
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end component;
component funcdecode
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end component;
signal op: std_logic_vector (31 downto 0);
signal aluop: std_logic_vector (1 downto 0);
signal func: std_logic_vector (5 downto 0);
signal aluoperation: std_logic_vector (2 downto 0);
signal memtoreg: std_logic;
signal memwrite: std_logic;
signal branch: std_logic;
signal alusrc: std_logic;
signal regdst: std_logic;
signal regwrite: std_logic;
signal pcsrc: std_logic;
signal regdest: std_logic_vector (4 downto 0);
signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
signal signunitBUS: std_logic_vector (31 downto 0);
signal memReadData: std_logic_vector (31 downto 0);
signal destdata: std_logic_vector (31 downto 0);
signal srcdata1: std_logic_vector (31 downto 0);
signal srcdata2: std_logic_vector (31 downto 0);
signal nulbit: std_logic;
signal pcBUSplus: std_logic_vector (31 downto 0);
signal pcBUS: std_logic_vector (31 downto 0);
signal Value32_4: std_logic_vector (31 downto 0);
signal add1cBus: std_logic_vector (31 downto 0);
signal add2cBus: std_logic_vector (31 downto 0);
signal Bit2ShiftBus: std_logic_vector (31 downto 0);
signal Value1_0: std_logic;
signal nullbit: std_logic;
signal globalCPUC: std_logic;
signal reset: std_logic;
begin
funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite);
mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);
signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);
add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);
pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUC, reset=>reset);
alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16), reset=>reset, clk=>globalCPUC);
sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData, clk=>globalCPUC, reset=>reset);
prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op, clk=>globalCPUC);
pcsrc <= nullbit and branch;
Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
Value1_0 <= '0';
reset <= '1' after 0 ns, '0' after 2 ns;
globalCPUC <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns, '1' after 6 ns, '0' after 7 ns, '1' after 8 ns, '0' after 9 ns, '1' after 10 ns;
end;
|
-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04
library ieee;
use ieee.std_logic_1164.all;
entity rslatch is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of rslatch is
begin
q <= (r nor p) and not reset;
p <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity clktriggeredrslatch is
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of clktriggeredrslatch is
component rslatch
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
p: inout std_logic;
reset: in std_logic
);
end component;
signal e, d: std_logic;
begin
rs: rslatch PORT MAP (r=>e, s=>d, q=>q, reset=>reset);
d <= c and s;
e <= c and r;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dlatch is
component clktriggeredrslatch
port (
r: in std_logic;
s: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end component;
signal e, f: std_logic;
begin
clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q, reset=>reset);
e <= d;
f <= not d;
end;
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d: in std_logic;
c: in std_logic;
q: inout std_logic;
reset: in std_logic
);
end;
architecture behaviour of dff is
component dlatch
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal e, a, b: std_logic;
begin
d1: dlatch PORT MAP (c=>a, d=>e, q=>q, reset=>reset);
d2: dlatch PORT MAP (c=>b, d=>d, q=>e, reset=>reset);
a <= not c;
b <= c;
end;
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end;
architecture behaviour of reg32 is
component dff
port (
q: inout std_logic;
d: in std_logic;
c: in std_logic;
reset: in std_logic
);
end component;
signal p: std_logic_vector (31 downto 0);
begin
gen_reg: FOR i in 31 downto 0 generate
dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c, reset=>reset);
q(i) <= p (i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX32_2_1 is
begin
MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity MUX5_2_1 is
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end;
architecture behaviour of MUX5_2_1 is
begin
MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
c (i) <= (a (i) and not x) or (b (i) and x);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1, reset=>reset);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2, reset=>reset);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
c1 <= en and clk and not regdest;
c2 <= en and clk and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regsrc2: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regsrc2: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regsrc2: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity registerset32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of registerset32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component registerset16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regsrc2: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
signal srcdata2_1: std_logic_vector (31 downto 0);
signal srcdata2_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
----------- SRAM
library ieee;
use ieee.std_logic_1164.all;
entity sram2_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram2_32 is
component reg32
port (
c: in std_logic;
d: in std_logic_vector (31 downto 0);
q: out std_logic_vector (31 downto 0);
reset: in std_logic
);
end component;
component MUX32_2_1 is
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal q1: std_logic_vector (31 downto 0);
signal q2: std_logic_vector (31 downto 0);
signal c1, c2: std_logic;
begin
reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1, reset=>reset);
reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2, reset=>reset);
srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
c1 <= en and clk and not regdest;
c2 <= en and clk and regdest;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram4_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram4_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram2_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic;
regdest: in std_logic;
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
ram1: sram2_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (0), en=>en1, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
ram2: sram2_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (0), en=>en2, destdata=>destdata, regdest=>regdest (0), reset=>reset, clk=>clk);
en2 <= regdest (1) and en;
en1 <= not regdest (1) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram8_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram8_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram4_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (1 downto 0);
regdest: in std_logic_vector (1 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
ram1: sram4_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
ram2: sram4_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (2) and en;
en1 <= not regdest (2) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram16_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram16_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram8_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (2 downto 0);
regdest: in std_logic_vector (2 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
ram1: sram8_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
ram2: sram8_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (3) and en;
en1 <= not regdest (3) and en;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram32_32 is
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end;
architecture behaviour of sram32_32 is
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component sram16_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (3 downto 0);
regdest: in std_logic_vector (3 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal c1, c2: std_logic;
signal en1, en2: std_logic;
signal srcdata1_1: std_logic_vector (31 downto 0);
signal srcdata1_2: std_logic_vector (31 downto 0);
begin
mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
ram1: sram16_32 PORT MAP (srcdata1=>srcdata1_1, regsrc1=>regsrc1 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
ram2: sram16_32 PORT MAP (srcdata1=>srcdata1_2, regsrc1=>regsrc1 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0), reset=>reset, clk=>clk);
en2 <= regdest (4) and en;
en1 <= not regdest (4) and en;
end;
-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of fulladder is
begin
c <= a xor b xor s;
t <= (a and b) or ((a or b) and s);
end;
library ieee;
use ieee.std_logic_1164.all;
entity ripplecarrychainadder32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end;
architecture behaviour of ripplecarrychainadder32 is
component fulladder
port (
a: in std_logic;
b: in std_logic;
c: out std_logic;
s: in std_logic;
t: out std_logic
);
end component;
signal x: std_logic_vector (32 downto 0);
begin
fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
END GENERATE;
t <= x (32) ;
x (0) <= s;
--fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
--fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
--fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
--fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity com32 is
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of com32 is
begin
com_connect: FOR i IN 31 DOWNTO 0 GENERATE
y (i) <= not x (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity neg32 is
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of neg32 is
component com32
port (
x: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end component;
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
signal c: std_logic_vector (31 downto 0);
signal d: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
d (i) <= '0';
END GENERATE;
s <= '1';
com: com32 PORT MAP (x=>a, y=>c);
add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;
library ieee;
use ieee.std_logic_1164.all;
entity sub32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end;
architecture behaviour of sub32 is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component neg32
port (
b: out std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
signal x: std_logic_vector (31 downto 0);
signal s: std_logic;
begin
neg: neg32 PORT MAP (a=>a, b=>x);
add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
s <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity and32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of and32 is
begin
genand32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) and a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sram is
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
clk: in std_logic;
reset: in std_logic
);
end;
architecture behaviour of sram is
component sram32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
begin
sram1: sram32_32 PORT MAP (en=>en, clk=>clk, reset=>reset, srcdata1=>readdata, destdata=>writedata, regsrc1=>addrs (4 downto 0), regdest=>addrs (4 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
entity prom is
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
clk: in std_logic
);
end;
architecture behaviour of prom is
begin
readdata <= ('0','0','1','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0','0','0','0','0','0','0','0','0','1','1','1') when addrs (4 downto 0) = ('0','0','0','0','0') else ('0','0','1','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1') when addrs (4 downto 0) = ('0','0','1','0','0') else ('0','0','1','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0','0','0','0','0','0','1','1','1','1','1','1') when addrs (4 downto 0) = ('0','1','0','0','0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z4, z3, z2, z1: std_logic;
signal x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
z1 <= (not s (2) and s (1) and not s (0));
z2 <= (s(2) and s(1) and not s(0));
z3 <= (not s (2) and not s (1) and not s (0));
z4 <= (not s (2) and not s (1) and s (0));
--
-- z4 z3 z2 z1 x3 x2 x1
-- 0 0 0 1 0 x 0
-- 0 0 1 0 0 x 1
-- 0 1 0 0 1 0 x
-- 1 0 0 0 1 1 x
-- x3 <= z3 or z4
-- x2 <= z3
-- x1 <= z2
x3 <= z3 or z4;
x2 <= z4;
x1 <= z2;
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
signal x2: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
x2 <= not opcode (5) and not opcode (4) and not opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1; ---? Bei immidiate - 15:15 - ist aber x1
regwrite <= x0 or x1 or x2;
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
-- x1 x2 alup
-- 0 0 xx
-- 0 1 0
-- 1 0 0
-- 1 1 0
aluop (1) <= not (x2 or x1);
aluop (0) <= not (x2 or x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x1, x0: std_logic;
begin
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
x1 <= (not aluop (1) and not aluop (0));
aluoperation (2) <= x0;
aluoperation (1) <= x0 or x1;
aluoperation (0) <= x0;
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
end;
library ieee;
use ieee.std_logic_1164.all;
entity Bit2Shift is
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of Bit2Shift is
begin
b (31 downto 2) <= a (29 downto 0);
b (1 downto 0) <= ('0', '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity signunit is
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of signunit is
begin
b (31 downto 16) <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0');
b (15 downto 0) <= a;
end;
library ieee;
use ieee.std_logic_1164.all;
entity mips32 is
port (
globalCPUCLK: in std_logic
);
end;
architecture behaviour of mips32 is
component registerset32_32
port (
srcdata1: out std_logic_vector (31 downto 0);
srcdata2: out std_logic_vector (31 downto 0);
destdata: in std_logic_vector (31 downto 0);
regsrc1: in std_logic_vector (4 downto 0);
regsrc2: in std_logic_vector (4 downto 0);
regdest: in std_logic_vector (4 downto 0);
en: in std_logic;
clk: in std_logic;
reset: in std_logic
);
end component;
component ALU
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (2 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end component;
-- 4 x MUX
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
component MUX5_2_1
port (
c: out std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
a: in std_logic_vector (4 downto 0);
x: in std_logic
);
end component;
-- befehlszaehler, addierer + 4 u Sprung 2x Addierer
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component Bit2Shift
port (
a: in std_logic_vector (31 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component signunit
port (
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (31 downto 0)
);
end component;
component sram
port (
en: in std_logic;
addrs: in std_logic_vector (31 downto 0);
writedata: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
reset: in std_logic;
clk: in std_logic
);
end component;
component prom
port (
addrs: in std_logic_vector (31 downto 0);
readdata: out std_logic_vector (31 downto 0);
clk: in std_logic
);
end component;
component reg32
port (
q: out std_logic_vector (31 downto 0);
d: in std_logic_vector (31 downto 0);
c: in std_logic;
reset: in std_logic
);
end component;
component opdecode
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end component;
component funcdecode
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (2 downto 0)
);
end component;
signal op: std_logic_vector (31 downto 0);
signal aluop: std_logic_vector (1 downto 0);
signal func: std_logic_vector (5 downto 0);
signal aluoperation: std_logic_vector (2 downto 0);
signal memtoreg: std_logic;
signal memwrite: std_logic;
signal branch: std_logic;
signal alusrc: std_logic;
signal regdst: std_logic;
signal regwrite: std_logic;
signal pcsrc: std_logic;
signal regdest: std_logic_vector (4 downto 0);
signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
signal signunitBUS: std_logic_vector (31 downto 0);
signal memReadData: std_logic_vector (31 downto 0);
signal destdata: std_logic_vector (31 downto 0);
signal srcdata1: std_logic_vector (31 downto 0);
signal srcdata2: std_logic_vector (31 downto 0);
signal nulbit: std_logic;
signal pcBUSplus: std_logic_vector (31 downto 0);
signal pcBUS: std_logic_vector (31 downto 0);
signal Value32_4: std_logic_vector (31 downto 0);
signal add1cBus: std_logic_vector (31 downto 0);
signal add2cBus: std_logic_vector (31 downto 0);
signal Bit2ShiftBus: std_logic_vector (31 downto 0);
signal Value1_0: std_logic;
signal nullbit: std_logic;
signal globalCPUC: std_logic;
signal reset: std_logic;
begin
funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite);
mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);
signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);
add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);
pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUC, reset=>reset);
alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16), reset=>reset, clk=>globalCPUC);
sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData, clk=>globalCPUC, reset=>reset);
prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op, clk=>globalCPUC);
pcsrc <= nullbit and branch;
Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
Value1_0 <= '0';
reset <= '1' after 0 ns, '0' after 2 ns;
globalCPUC <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns, '1' after 6 ns, '0' after 7 ns, '1' after 8 ns, '0' after 9 ns, '1' after 10 ns;
end;
|
https://opencores.org/projects/plasma/opcodes
Vorzeichenerweiterungseinheit:
16 Bit relative Werte
16 Bit Zweierkomplement. Betrag: 15 Bit + 1 Bit Vorzeichen 15 Bit: 16384 = 16k
Vor und zurueck oder positiv negativ immidiate
Aber 16 Bit Wert. wird zu 32, z.B. fuer Addition in ALU Vorzeichenerweiterungseinheit: 16 bit unsigned kein problem zu 32 unsigned aber 16 Bit zweierkomplement => vorzeichenerweiterungseinheit
Befehle weiss ich auswendig
lb, lbu: laden eines bytes lh, lhu: laden eines halbwortes lw ld* la* li*
sb sh sw sd*
Lade und Speicherarchitektur
Laden - Load - Speicher-Register Speichern - Store - Register-Speicher MOVE - Register-Register li, ldi, ... Laden eines direktwerts in ein Register, Konstante im Code
sb: Nicht speichern einer Konstante, sondern
rs, rt - immidiate
i-typ Befehl
R-Typ: rs, rt, rd - 2 x Quell Register, 1 x ziel I-Typ: 1 Quellregister, 1 Zielregister, 1 zusaetzliche Konstante Rel Wert J-Typ: J-Typ - Jump: Konstanter Langer Direktwert - Bei spruengen, nicht relativ vom aktuellen PC, sondern absoluter wert
I-Typ, bei lbu: nicht Konstante laden, - bu und b und ..., sondern Speicherstelle von der groesse byte, an der Stelle, rt - muss addressiert werden, rs - ziel Register, rt: Addresse im RAM von wo aus geladen und b - Speichergroesse, Konstante? Verschiebewert!
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
signal x2: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
x2 <= not opcode (5) and not opcode (4) and not opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1; ---? Bei immidiate - 15:15 - ist aber x1
regwrite <= x0 or x1 or x2;
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
-- x1 x2 alup
-- 0 0 xx
-- 0 1 0
-- 1 0 0
-- 1 1 0
aluop (1) <= not (x2 or x1);
aluop (0) <= not (x2 or x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (3 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;s
begin
-- 00 add
-- 01 sub
-- 10 nutze das func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
-- x1 : add
-- x2 : sub
-- x3 : and
-- x4 : or
-- x5 : nor
-- x6 : slt
-- x7 : xor
-- x8 : sll
-- x9 : srl
-- x10: sra
-- x11: mult
-- x12: div
-- aluop: 10 ...
-- ... func:
-- 100 000 - add 4 0
-- 100 010 - sub 4 2
-- 100 100 - and 4 4
-- 100 101 - or 4 5
-- 100 111 - nor 4 7
-- 101 010 - slt 5 2
-- 100 110 - xor 4 6
-- 000 000 - sll 0 0
-- 000 011 - sra 0 3
-- 000 010 - srl 0 2
-- 011 000 - mult 3 0
-- 011 010 - div 3 2
x1 <= (not aluop (1) and not aluop (0)) or
(alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- add
x2 <= (not aluop (1) and aluop (0)) or
(alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- sub
x3 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0); -- and
x4 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0); -- or
x5 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slt
x6 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0); -- nor
x7 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0); -- xor
x8 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- sll
x9 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sra
x10 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- srl
x11 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0); -- mult
x12 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0); -- div
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- vier bit
-- 0010 - add
-- 0110 - sub
-- 0000 - and
-- 0001 - or
-- 1111 - slt
-- selber erweitert:
-- x
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
aluoperation (3) <= x0 or x9 or x10 or x11 or x5
aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5
aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5
aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5
end;
|
Zu dem Blockschaltbild -
1.) R-Typ 2.) I-Typ 3.) J-Typ
So weit ich hier sehe, ist kein J-Typ implementiert
1.) R-Typ: Register 2.) I-Typ: Immidiate 3.) J-Typ: Jump Absolut wert im speicher zu dem gesprungen wird
Klassischer Additionsbefehl
1.) Intel: ADD AX, BX
2.) MIPS32: add 
r1,
r0, r1
Addition:
x = 5 + 4 9 = 5 + 4 c = a + b
1.) zwei Quelloperanten 2.) Ein Zieloperant
Vier Grundrechenarten auf die ganzen und natuerlichen Zahlen 1.) Addition 2.) Subtraktion 3.) Multiplikation 4.) Division
3 Operanten/Operanden! - 2 quell, 1 Ziel
Operantenschreibweise beim Computer
1.) zwei Operanten schreibweise 2.) drei Operanden schreibweise
intel x86/i386/i586/amd64, Atmel Atmega 8: 2 - Einer der Quelloperanten entspricht dem Ziel MIPS32: 2 Quelloperand, ein Ziel
Kommt auf das gleiche raus
Mikroarchitektur: Implementierung der CPU - egal, etwa: Heimlich kodiert im befehl, bei 2 Operanden, als 3 Oder sie loesen das Intern, sie koennen beliebig Schaltwerke bauen, oder schaltung, die schreibt und laedt, egal
Vorsicht!
Akkumulatorarchitektur
1.) Ein Operanden schreibweise
ausgangspunkt ist der Akku - besonders ausgezeichnetes, Allzweckregister
Akku: Ein Operand, der andere ist immer der Akku
wie kommt das da rein: Datentransferbefehl
vor jeder Arithmetischen Operation immer ein Datentransferbefehl fuer den akku
2.) Stack und Kellerarchitektur - 8087 intel
PUSH r0 PUSH r1 ADD
Kein Operand. nur bei Push und Pop landen auf Stack, Add, die letzten beiden Werte oben auf Stack, ziel wieder auf Stack
1.) R-Typ typisch arithemtisch
1.) Ein Ziel, zwei quellen - alles Register
r: Register
rs: Quelloperand - r Register, s source rt: Quelloperand - r Register, t source - man kann schreiben s1, s2, aber das mehr zeichen => s/t rd: Zieloperand - r Register, d - destination
befehl:
Opcode rs, rt, rd
Befehl: 32 Bit Opcode: 6 Bit rs: 5 Bit rt: 5 Bit rd: 5 Bit
da, es 32 Bit register gibt, genuegen 5 Bit, um alle Register an zu sprechen,
2^5= 32
Bit 31 bis Bit 26: OpCode Bit 25 bis Bit 21: rs Bit 20 bis Bit 16: rt Bit 15 bis Bit 11: rd ...
Der Registersatz, hat
1.) Daten 2.) register Select - Entspricht - Addresse im RAM kann 32 Werte annehmen, fuer 32 Register,
2^5
weil, im Befehl: 2 Quellregister, 1 Zielregister ...
Die Werte, mit denen beim MIPS32 gehandelt werden, sind 32 Bit breit === 4G
Das sind die Werte selber, auf die Operiert wird, uebliche groessen beim Computer sind
4 Bit - 1 Nibble - absolut selten in der Vergangenheit 8 Bit - 1 Byte - Mikrocontroller 16 Bit - 1 Wort - zum Beispiel x86, erster IBM PC, ohne MMU und speicherschutz, vor Linux, Minix/MS-DOS 32 Bit - 1 Doppelwort - i386, IBM PC nachfolger, mit MMU und Paging, auf das Linus Torvalds Linux gemacht hat, mit Speicherschutz, MMU 64 Bit - amd64 - moderne Computer, intel core i3, i5, ...
Gut, operieren z.B. MIPS32, auf Werte, die 32 Bit breit sind 0 .. 4G -1,
Werte: inhalte Wo liegen die Werte: Speicherplatz, register
Speicherplatz: Addresse Register: Registerselect
32 register - heisst, Registerselect 5 Bit - 32 Register im Registersatz ansprechbar
2^5= 32 Es sind in 32 Register, werte mit 32 bit ansprechbar, die Register selber: Anzahl 32
2^5
rs, rt, rd
jeweils 5 Bit, um jeweils eines der 32 Register aus zu waehlen, die jeweils werte mit 32 bit kodiert enthalten, 0 .. 4G - 1
R-Typ befehl
31 .. 26: Opcode (immer 6 Bit) 25 .. 21: rs (5 Bit) 20 .. 16: rt (5 Bit) 16 .. 11: rd (5 Bit) 11 .. 6: 5 .. 0: func feld
OK - Datenpfad
Prozessor:
1.) Rechenwerk 2.) Leitwerk
komplexes schaltwerk
1.) Operationswerk 2.) Steuerwerk
Einfaches Schaltwerk
1.) Schaltwerk 2.) uebergangsschaltnetz - zum naechsten Zustand 3.) Ausgangsschaltnetz - fuer die Ausgabe
komplexes schaltwerk
1.) Operationswerk: Kann Register enthalten 2.) Steuerwerk
Prozessor:
1.) Rechenwerk: Universelles Operationswerk 2.) Leitwerk: Umschaltbares Steuerwerk
1.) Rechenwerk: Komplexes Schaltwerk: Kann register enthalten Rechenwerk: ALU + Registersatz 2.) umschaltbares Steuerwerk: holt Befehle aus dem Speicher, Befehle genuegen im gegensatz zu den Eingaben beim einfachsten Schaltwerk oder Komplexen Schaltwerk, in jedem Fall sehr einheitlichen Definitionen/...
Rechenwerk = universelles Operationswerk Rechenwerk = ALU + Registersatz
R-Typ befehl: 3 operanden
c = a + b $r3 = $r1 + $r2 add $r3, $r1, $r2 |
1.) Datum im Register selber 2.) Auswahl des Register
Macht: 6
1.) Zwei quellregister 2.) ein Ziel register macht 3
1.) Datum selber, 32 Bit 2.) Register Select, Register Auswahl, 5 Bit macht 2
2*3 = 6
Jetzt Addition findet auf zwei Quellregister statt und landet im Zielregister Die Operation findet in der ALU statt
Zwei quellregister aus dem Registersatz werden selektiert und ihre Werte werden in der ALU arithmetisch logisch verarbeitet verknuepft und landen als Wert im Registersatz naemlich dort im Zielregister, selektiert wie jedes Register, mit 5 Bit, ankommt, ein 32 Bit Wert
Gut:
Registersatz -> ALU -> Registersatz
Datenpfad, R-Typ
4 x MUX!
MUX gesteuert ueber - Befehlsdekodierer Ich nenne sie
MUX1, MUX2, MUX3, MUX4
Nummierung: Von west nach ost - links nach rechts Norden nach sueden, oben nach unten
An Zustandselementen - Register, Speicher - WE
WE - Write enable
WE - Writenable: HIGH, in das Zustandselement wird geschrieben Jederzeit landen die Daten sowohl an den Eingaengen vom Speicher, ... ... als auch von registern
blos: WE - HIGH - am registersatz, daten uebernehmen WE - HIGH am speicher, daten im Speicher uebernehmen
dadurch dass z.B. HIGH am Registersatz, LOW am Speicher, WE - Daten im Registersatz uebernehemen, nicht im Speicher
MemWrite: 1 Bit: Befehlsdekoder - Speicher, speicher: WE - heisst, Memory Write RegWrite: 1 Bit: Befehlsdekoder - Registersatz, we - heisst, Registerset write
so, ob daten, hier und Dort uebernehmen, die am gleichen Datenpfad, ausgang letzte Komponente, WE ausgang: Entweder datum hi oder hot - MUX
MUX: 1 Bit, Steuerbit s
s = 0, A, Hi s = 1, B, Hot
Gut: R-Typ
Register-Select === Name - lese-Register, Quelloperand === Name - Schreiberegister, zieloperand
op rs rt rd sa func
rs: Bit 25 bis Bit 21 geht in Lese-Register-1 Registersatz, Auswahl rt: Bit 20 bis Bit 16 geht in Lese-Register-2 registersatz, auswahl
laesst
Lese-daten-1 - 32 bit wert aktiv werden, sind sie so oder so, werden selektiert Lese-Daten-2 - 32 Bit wert aktiv werden, sind sie so oder so
Jetzt kommt MUX2, MUX2: ALUSrc
Hi und Hot
0: Hi: Operand 2 - ist Lese-Daten-2 ALU, 2. Quelloperand
add $r0, $r1, $r4 indem Falle $r4 |
ALU-Src
src: Quelle
ALU-src- Quelle des 2. ALU Quelloperanden, 1. immer aus Registersatz, Lese-Daten-1
ALU-src: MUX, Selektion: Entweder aus Registersatz, vor der ALU, ALU, Src, woher, Quelle, bei ALU 1. Operand, immer Registersatz, zweiter: I-Typ Befehl
Gut: R-Typ:
Jetzt Ergebnis an ALU, MUX 3. Moegliche Alternative:
Store
Load/Store
I-Typ
I-Typ braucht 2 Register, nicht wie gemeint, 1 und eine Addresse wird gleich erklaert
Die Daten der ALU, Zieloperand, gehen gleichzeitig
1.) In den Datenspeicher 2.) MUX3
Da nicht in Datenspeicher, WE von Datenspeicher = 0, daten nicht im Datenspeicher uebernommen
MUX3: hi, MemToReg
MemToReg: Heisst: Memory 2 Register, als from Memory to register?
1.) I-Typ: Speichern 2.) I-Typ: Laden
oder
1.) I-Typ: Speichern 2.) I-Typ: Laden 3.) I-Typ: Add Immidiate
I-Typ, nachher, aber, waehrend einer I-Typ, Speichern, muss bei Speichern Addresse, dann waere WE enable = 1, von Speicher 2. I-Typ lesen von speicher, aber jetzt MUX3, = 1, hot, jetzt lesedaten vom Speicher
nach MUX3, in schreibedaten, WE von Registersatz = 1, von Befehlsdekodierer u. schreiberegister, register select von zieloperand, rd - 3. operand
Aber Vorsicht MUX 1, es kaeme zu kollision
bei i-typ 2 Register, Befehl
wenn sie 3 Register haben, 5 bit Select
5 Bit + 5 Bit + 5 Bit
brauchen sie 5 Bit mehr, als bei 2 Registern select
5 Bit + 5 bit
31 .. 26: opcode 25 .. 21: rs 20 .. 16: rt 15 .. 11: rd .. bei 3 31 .. 26: opcode 25 .. 21: rs 20 .. 16: rt 15 .. 0: immidiate: 16 Bit konstante aber kein register ..
Deswegen steht der letzte Operand bei R-Typ, das Ziel bei 15 .. 11, bei I-Typ, bei 20 .. 16 hier MUX1, entweder 20:16 oder 15 .. 11 fuer zieloperand, gesteuert ueber: RegDst - Registerdestination, Befehlsdekodierer
R-typ: opcode rs rt rd sa func I-Typ: opcode rs rt immidiate
immidiate, 16 bit
beim ersteren
i-typ:
zwei Register, Ziel und Quelle und ein 16 Bit direktwert
Im Gegensatz zu einem j-Typ, gibt es keinen 32 - 6 = 26 Bit Direkten wert Dieser wert ist ausser bei absoluten sprungzielen unbequem, weil wir mit 32 bit rechnen, auch noch 16 bit werte haben. Der nur bei absoluten werten
so. I-Typ: 16 Bit breiter immidiate Wert 16 Bit = 32k Werte.
Dieser ist zweier Komplement, zweier komplement = 1 Komplement +1
einer komplement 1010 = 0101 zweier komplement 0101 +1 = 0110
Oder positive ganzzahl, wenn Vorzeichen gesetzt, dann 2er Komplement wenn nicht 15 bit positive Ganzzahl, natuerliche
warum Vorzeichenerweiterungseinheit?
weil 16 Bit, aber nachher 32
Wenn man 2er komplement hat, so oder so und/oder natuerliche, 16 Bit man muss aufpassen bei fuellen oben MSB... zu 32 bit
I-Typ: Speichern, ßchreiben store
16 Bit immidiate von Befehl
31 .. 26: Opcode 25 .. 21: rs 21 .. 16: rt 15 .. 0: immidiate
15 .. 0 immidiate geht durch vorzeichenerweiterungseinheit, wird 32 Bit
jetzt kommt MUX2, ALU-Src, dies Mal, von Vorzeichenerweiterungseinheit, nicht Registersatz, Op2
wird mit operand1, addiert
das ist Addressierung: Register mit festen relativem wert
Register + Fester Relativer Wert
Operand 1, register satz, wie immer geht, in ALU, muss + immidiate Geht zusammen Addition in ALU, Zieloperand, dies Mal addresse vom Arbeitsspeicher, datenspeicher, Heap, bildet Addresse jetzt WE Write enable von Datenspeicher = 1, in Datenspeicher wird geschrieben, blos what?
Register 2 - operand 2, direkt rein.
Store - Addresse im RAM und Register, fertig
Die Addresse im RAM aus immdiate und Register, 2, damit Ende Rest regelt sich, dass WE bei registersatz nicht aktiv, auch, wenn daten dahin
Load: wie gerade eben.
Hier zwei Moeglichkeiten, gaebe es:
Wie bei R-Typ addiere ich beide quellregister, und tue sie in die ALU, und sie bilden addresse Addresse vom RAM, immer von ALU-Ergbnis Operand 3 Oder wie gerade eben, store
immdiate immdiate durch vorzeichenerweiterungseinheit MUX2 = 1 –> Immidiate + lese-daten 1, registersatz, Addresse,
aber, WE am RAM = 0. Dafuer MemToReg, MUX3, = 1. Bedeutet, jetzt nicht ALU-Ergebnis in registersatz, sondern RAM und jetzt wie gehabt, wie vorher
Was die Spruenge und Befehle im Programmspeicher betrifft
Vorsicht!
neumann: daten und Programmspeicher gemeinsam Harvard: Gemeinsam
Atmega8: Harvard: SRAM und Programmspeicher Programmspeicher nicht fluechtig
Ganz anderer Pfad, Spruenge Auch Immdiate
Aber das zeigt nich in den Datenspeicher
Programmablauf:
Befehl, Befehl, Befehl, ...
Da Befehl, 32 Bit
Speicher 4 bit, immer +4, +4, +4, Programmzaehler
Befehlszaehler -> Addierer 1, +4 jetzt MUX4,
MUX4, ist Branch
Wozu? normaler Befehl +4, +4, ...
Ich muss wissen, will ich verzweigen oder weiter gerade aus. Wegen Bedingten Spruengen?
Nein Generell. Unabhaengig, ob bedingt oder nicht Bei verzweigungen und Spruengen liegt die Addresse nicht an der naechsten stelle. Sie steht im Befehl. bei normalen Befehlen nicht, immr +4
Deswegen MUX4: Befehlsdekodierer, Branch
Hueh: 0: +4 Hot: Vorzeichenerweiterungseinheit, - immdiate, positiv negativ zu 32 Bit Dann um 2 nach links
warum? Bei direktwerten nicht, im Befehl, Addition, aber befehl kann nicht an Stelle
n+1, n+2, n+3 liegen, weil Befehl immer 4 byte, also shift nach links
Dann geht das in addierer 2. Warum?
Zunaechst spruenge sind relativ. Das heisst, zum aktuellen Befehlszaehler, aber das ist irrefuehrend Da der naechste Befehl ohne Sprung, +4, +4, +4 geht es immer durch addierer 1. +4
jetzt koennte man die Verzweigung zum aktuell letzten Befehlszaehler addieren, in Addierer 2 Tatsaechlich geht der PC immer durch Addierer 1, +4 und jetzt relativ
immdiate geht durch vorzeichenerweiterung, 16 nach 32 Bit, dann « 2 nach links, wegen 4 Byte Grenze, dann addierer, relativ dazu addieren, aber zu addierer 1 +4, fertig
jetzt kommt MUX4, und macht die verzweigung
Befehle
lb lbu lh lhu lw ld* la* li* sb sh sw sd* add addi addiu sub mult multu div divu and andi or ori xor xori
Verzweigungen:
breq, brne blt, ble bgt, bge
beqe*, bnez* bgtz, bgez bltz, blez
das eine mit entspricht null, das andere vergleich Register, Register
Zu gegebener Massen, war da ein Fehler drin, den jeder Intel Programmierer kennt
2^16 = 64k |
Jedes Intel Segment ist 64k. das weiss, jeder, das liegt daran, der fehler, dass ich die 2er Potenzen bis 8192 auswendig kenne
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192
und jetzt wird es spannend, folgen sie meinen Uebungen, Binaerzahlen um zu rechnen, rechne ich bei Bit 14 und Bit 15 immer
8192*2 8192*4
seltsam, 8192 ist Bit 13 Und 16384 Das weiss ich noch auswendig 14 ebenso wie 32k bit 15
32k bit 15, ist Bit 15, 32k, warum dann 64k
weil 64 k ist 1111 1111 1111 1111 32 k: 1000 0000 0000 0000
rechnet man 0111 1111 1111 1111
kommt man auf 32k-1, zusammen mit der 0, 32k 0111 1111 1111 1111
kommt man auf 2x32k = 64k
Das ist in der Eile passiert, tut mir leid, jeder Intel Programmer weiss, die Segmente sind 64k
Das ist nicht so besonders spannend, meine Erklaerungen zum MIPS32, sind gut und absolut richtig
Ansonsten muss man sich nur noch merken
1.) Der Opcode ist immer 6 Bit breit - also das, was entscheidet, welcher Befehl kommt, im 32 Bit Befehl 2.) Es gibt: Befehlsdekodierer 3.) Es gibt: Funktionsdekodierer
Der Befehlsdekodierer ist fuer das Grobe ausserhalb der ALU zustaendig, WE an Speicher und Registersatz Der Funktionsdekodierer wird von dem Befehsldekodierer mit gesteuert
Man koennte ihn wohl auch gleich im befehlsdekodierer unterbringen
Er steuert die ALU feiner
1.) Es gibt eine Grobe Steuerung fuer das wichtigste 2.) eine feine Steuerung, fuer das besondere
1.) Der Befehlsdekodierer erkennt einen befehl fuer die ALU - R-Typ, 2 Operanden, arithmetisch/logisch 2.) Das teilt er dem Funktionsdekodierer mit, und 2 mit 2 Bit
00 - addition 01 - subtraktion 10 - nutze das func-feld 11 - n/a
na: not applicable/not accessable = nicht machbar = unsinn nc: not connected, an bauteilen
Der R-Typ Befehl
31 .. 26: opcode 25 .. 21: rs 20 .. 16: rt 15 .. 11: rd 10 .. 6: sa 6 .. 0: func
func: Im Befehl genaue Steuerung fuer den Funktionsdekodierer
Zwischen Befehlsdekodierer und Funktionsdekodierer 2 Bit
00 - immer Addition - Addition, das groebste, essentiell, rudimentaer 01 - subtration ebenso
Aber Arithmetisch logisch:
Addition, Subtraktion, multiplaktion, division AND, OR, XOR, NOT, NOR SHIFT RIGHT, LEFT, ROTATE RIGHT, LEFT ...
Deswegen:
10 - an Befehlsdekodierer: func feld
Das geht so:
100 000 - add - dieser ist redudant - 00 beudetet immer add, zwischen (1) und (2) 10 nutze func feld, hier noch mal add 100 010 - sub 100 100 - and 100 101 - or 101 010 - slt
100 000 - 4 0 100 010 - 4 2 100 100 - 4 4 100 101 - 4 5 101 011 - 5 2
Das kann man sich nicht merken. Also wer linux kann, kann sich rechte merken
rwx
111 - rwx 110 - rw 101 - rx 100 - r 011 - wx 010 - w 001 - x 000 - nichts
da kann man sich 4 0, 4 2... noch merken
vom Funktionskekodier an ALU
001 add 110 sub 000 and 001 or 111 slt
das ist vom Funktionsdekodier an ALU Das andere func Feld im Befehl und 2 Bit Befehlsdekodierer Funktionsdekodier und 5 Bit Opcode
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z11, z10, z9, z8, z7, z6, z5, z4, z3, z2, z1, z12: std_logic;
signal x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cmux3: std_logic_vector (31 downto 0);
signal cmux4: std_logic_vector (31 downto 0);
signal cmux5: std_logic_vector (31 downto 0);
signal cmux6: std_logic_vector (31 downto 0);
signal cmux7: std_logic_vector (31 downto 0);
signal cmux8: std_logic_vector (31 downto 0);
signal cmux9: std_logic_vector (31 downto 0);
signal cmux10: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cxor, b=>cnor, c=>cmux3, x=>x3);
mux4: MUX32_2_1 PORT MAP (a=>cmult, b=>cdiv, c=> cmux4, x=>x4);
mux5: MUX32_2_1 PORT MAP (a=>csll, b=>csrl, c=>cmux5, x=>x5);
mux6: MUX32_2_1 PORT MAP (a=>csra, b=>cslt, c=>cmux6, x=>x6);
mux7: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>cmux7, x=>x7);
mux8: MUX32_2_1 PORT MAP (a=>cmux3, b=>cmux4, c=>cmux8, x=>x8);
mux9: MUX32_2_1 PORT MAP (a=>cmux5, b=>cmux6, c=>cmux9, x=>x9);
mux10: MUX32_2_1 PORT MAP (a=>cmux7, b=>cmux8, c=>cmux10, x=>x10);
mux11: MUX32_2_1 PORT MAP (a=>cmux9, b=>cmux10, c=>d, x=>x11);
x1 <= not z1 and z2;
x2 <= not z3 and z4;
x3 <= not z7 and z6;
x4 <= not z11 and z12;
x5 <= not x8 and x10;
x6 <= not x9 and x5;
x7 <= not x1 and x2;
x8 <= not x3 and x4;
x9 <= not x5 and x6;
x10 <= not x7 and x8;
x11 <= not x9 and x10;
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
xor1: xor32 PORT MAP (a=>a, b=>b, c=>cor);
div1: div32 PORT MAP (a=>a, b=>b, c=>cdiv);
nor1: xor32 PORT MAP (a=>a, b=>b, c=>cnor);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
sll1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csll);
sra1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csra);
srl1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csrl);
mult1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cmult);
slt1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cslt);
-- z s3s2s1s0
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
z3 <= (not s (3) and not s (2) and not s (1) and not s (0));
z4 <= (not s (3) and not s (2) and not s (1) and s (0));
z1 <= (not s (3) and not s (2) and s (1) and not s (0));
z7 <= (not s (3) and not s (2) and s (1) and s (0));
z12 <= (not s (3) and s (2) and not s (1) and not s (0));
z6 <= (not s (3) and s (2) and not s (1) and s (0));
z2 <= (not s (3) and s (2) and s (1) and not s (0));
z8 <= (not s (3) and s (2) and s (1) and s (0));
z9 <= (s (3) and not s (2) and not s (1) and not s (0));
z10 <= (s (3) and not s (2) and not s (1) and s (0));
z11 <= (s (3) and not s (2) and s (1) and not s (0));
z5 <= (s (3) and s (2) and s (1) and s (0));
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
signal x2: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
x2 <= not opcode (5) and not opcode (4) and not opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1; ---? Bei immidiate - 15:15 - ist aber x1
regwrite <= x0 or x1 or x2;
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
-- x1 x2 alup
-- 0 0 xx
-- 0 1 0
-- 1 0 0
-- 1 1 0
aluop (1) <= not (x2 or x1);
aluop (0) <= not (x2 or x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (3 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
begin
-- 00 add
-- 01 sub
-- 10 nutze das func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
-- x1 : add
-- x2 : sub
-- x3 : and
-- x4 : or
-- x5 : nor
-- x6 : slt
-- x7 : xor
-- x8 : sll
-- x9 : srl
-- x10: sra
-- x11: mult
-- x12: div
-- aluop: 10 ...
-- ... func:
-- 100 000 - add 4 0
-- 100 010 - sub 4 2
-- 100 100 - and 4 4
-- 100 101 - or 4 5
-- 100 111 - nor 4 7
-- 101 010 - slt 5 2
-- 100 110 - xor 4 6
-- 000 000 - sll 0 0
-- 000 011 - sra 0 3
-- 000 010 - srl 0 2
-- 011 000 - mult 3 0
-- 011 010 - div 3 2
x1 <= (not aluop (1) and not aluop (0)) or
(alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
x2 <= (not aluop (1) and aluop (0)) or
(alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
x3 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
x4 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
x5 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
x6 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
x7 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
x8 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
x9 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
x10 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
x11 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
x12 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- vier bit
-- 0010 - add
-- 0110 - sub
-- 0000 - and
-- 0001 - or
-- 1111 - slt
-- selber erweitert:
-- x
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;
end;
|
ALU
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component xor32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component nor32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component sll32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component srl32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z11, z10, z9, z8, z7, z6, z5, z4, z3, z2, z1, z12: std_logic;
signal x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cmux3: std_logic_vector (31 downto 0);
signal cmux4: std_logic_vector (31 downto 0);
signal cmux5: std_logic_vector (31 downto 0);
signal cmux6: std_logic_vector (31 downto 0);
signal cmux7: std_logic_vector (31 downto 0);
signal cmux8: std_logic_vector (31 downto 0);
signal cmux9: std_logic_vector (31 downto 0);
signal cmux10: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cxor, b=>cnor, c=>cmux3, x=>x3);
mux4: MUX32_2_1 PORT MAP (a=>cmult, b=>cdiv, c=> cmux4, x=>x4);
mux5: MUX32_2_1 PORT MAP (a=>csll, b=>csrl, c=>cmux5, x=>x5);
mux6: MUX32_2_1 PORT MAP (a=>csra, b=>cslt, c=>cmux6, x=>x6);
mux7: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>cmux7, x=>x7);
mux8: MUX32_2_1 PORT MAP (a=>cmux3, b=>cmux4, c=>cmux8, x=>x8);
mux9: MUX32_2_1 PORT MAP (a=>cmux5, b=>cmux6, c=>cmux9, x=>x9);
mux10: MUX32_2_1 PORT MAP (a=>cmux7, b=>cmux8, c=>cmux10, x=>x10);
mux11: MUX32_2_1 PORT MAP (a=>cmux9, b=>cmux10, c=>d, x=>x11);
x1 <= not z1 and z2;
x2 <= not z3 and z4;
x3 <= not z7 and z6;
x4 <= not z11 and z12;
x5 <= not x8 and x10;
x6 <= not x9 and x5;
x7 <= not x1 and x2;
x8 <= not x3 and x4;
x9 <= not x5 and x6;
x10 <= not x7 and x8;
x11 <= not x9 and x10;
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
xor1: xor32 PORT MAP (a=>a, b=>b, c=>cor);
div1: div32 PORT MAP (a=>a, b=>b, c=>cdiv);
nor1: xor32 PORT MAP (a=>a, b=>b, c=>cnor);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
sll1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csll);
sra1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csra);
srl1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csrl);
mult1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cmult);
slt1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cslt);
-- z s3s2s1s0
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
z3 <= (not s (3) and not s (2) and not s (1) and not s (0));
z4 <= (not s (3) and not s (2) and not s (1) and s (0));
z1 <= (not s (3) and not s (2) and s (1) and not s (0));
z7 <= (not s (3) and not s (2) and s (1) and s (0));
z12 <= (not s (3) and s (2) and not s (1) and not s (0));
z6 <= (not s (3) and s (2) and not s (1) and s (0));
z2 <= (not s (3) and s (2) and s (1) and not s (0));
z8 <= (not s (3) and s (2) and s (1) and s (0));
z9 <= (s (3) and not s (2) and not s (1) and not s (0));
z10 <= (s (3) and not s (2) and not s (1) and s (0));
z11 <= (s (3) and not s (2) and s (1) and not s (0));
z5 <= (s (3) and s (2) and s (1) and s (0));
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
|
Funktionsdekodierer:
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (3 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
begin
-- 00 add
-- 01 sub
-- 10 nutze das func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
-- x1 : add
-- x2 : sub
-- x3 : and
-- x4 : or
-- x5 : nor
-- x6 : slt
-- x7 : xor
-- x8 : sll
-- x9 : srl
-- x10: sra
-- x11: mult
-- x12: div
-- aluop: 10 ...
-- ... func:
-- 100 000 - add 4 0
-- 100 010 - sub 4 2
-- 100 100 - and 4 4
-- 100 101 - or 4 5
-- 100 111 - nor 4 7
-- 101 010 - slt 5 2
-- 100 110 - xor 4 6
-- 000 000 - sll 0 0
-- 000 011 - sra 0 3
-- 000 010 - srl 0 2
-- 011 000 - mult 3 0
-- 011 010 - div 3 2
x1 <= (not aluop (1) and not aluop (0)) or
(alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
x2 <= (not aluop (1) and aluop (0)) or
(alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
x3 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
x4 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
x5 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
x6 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
x7 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
x8 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
x9 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
x10 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
x11 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
x12 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- vier bit
-- 0010 - add
-- 0110 - sub
-- 0000 - and
-- 0001 - or
-- 1111 - slt
-- selber erweitert:
-- x
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;
end;
|
Richtig:
entity ALU is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic_vector (3 downto 0);
t: out std_logic;
nul: inout std_logic;
globalcarryflag: out std_logic
);
end;
architecture behaviour of ALU is
component ripplecarrychainadder32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
s: in std_logic;
t: out std_logic
);
end component;
component sub32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0);
t: out std_logic
);
end component;
component and32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component or32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component xor32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component nor32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component sll32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component srl32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component sra32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component slt32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component mult32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component div32
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end component;
component MUX32_2_1
port (
c: out std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
a: in std_logic_vector (31 downto 0);
x: in std_logic
);
end component;
signal z11, z10, z9, z8, z7, z6, z5, z4, z3, z2, z1, z12: std_logic;
signal x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1: std_logic;
signal csub: std_logic_vector (31 downto 0);
signal cor: std_logic_vector (31 downto 0);
signal cmux1: std_logic_vector (31 downto 0);
signal cmux2: std_logic_vector (31 downto 0);
signal cmux3: std_logic_vector (31 downto 0);
signal cmux4: std_logic_vector (31 downto 0);
signal cmux5: std_logic_vector (31 downto 0);
signal cmux6: std_logic_vector (31 downto 0);
signal cmux7: std_logic_vector (31 downto 0);
signal cmux8: std_logic_vector (31 downto 0);
signal cmux9: std_logic_vector (31 downto 0);
signal cmux10: std_logic_vector (31 downto 0);
signal cadd: std_logic_vector (31 downto 0);
signal cand: std_logic_vector (31 downto 0);
signal cmult: std_logic_vector (31 downto 0);
signal cdiv: std_logic_vector (31 downto 0);
signal csll: std_logic_vector (31 downto 0);
signal csrl: std_logic_vector (31 downto 0);
signal csra: std_logic_vector (31 downto 0);
signal cslt: std_logic_vector (31 downto 0);
signal cxor: std_logic_vector (31 downto 0);
signal cnor: std_logic_vector (31 downto 0);
signal sadd: std_logic;
signal d: std_logic_vector (31 downto 0);
begin
-- 010 add
-- 110 sub
-- 000 and
-- 001 or
-- 111 slt set less than
mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
mux3: MUX32_2_1 PORT MAP (a=>cxor, b=>cnor, c=>cmux3, x=>x3);
mux4: MUX32_2_1 PORT MAP (a=>cmult, b=>cdiv, c=> cmux4, x=>x4);
mux5: MUX32_2_1 PORT MAP (a=>csll, b=>csrl, c=>cmux5, x=>x5);
mux6: MUX32_2_1 PORT MAP (a=>csra, b=>cslt, c=>cmux6, x=>x6);
mux7: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>cmux7, x=>x7);
mux8: MUX32_2_1 PORT MAP (a=>cmux3, b=>cmux4, c=>cmux8, x=>x8);
mux9: MUX32_2_1 PORT MAP (a=>cmux5, b=>cmux6, c=>cmux9, x=>x9);
mux10: MUX32_2_1 PORT MAP (a=>cmux7, b=>cmux8, c=>cmux10, x=>x10);
mux11: MUX32_2_1 PORT MAP (a=>cmux9, b=>cmux10, c=>d, x=>x11);
x1 <= not z1 and z2;
x2 <= not z3 and z4;
x3 <= not z7 and z6;
x4 <= not z11 and z12;
x5 <= not x8 and x10;
x6 <= not x9 and x5;
x7 <= not x1 and x2;
x8 <= not x3 and x4;
x9 <= not x5 and x6;
x10 <= not x7 and x8;
x11 <= not x9 and x10;
and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
xor1: xor32 PORT MAP (a=>a, b=>b, c=>cor);
div1: div32 PORT MAP (a=>a, b=>b, c=>cdiv);
nor1: xor32 PORT MAP (a=>a, b=>b, c=>cnor);
sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
sll1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csll);
sra1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csra);
srl1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csrl);
mult1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cmult);
slt1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cslt);
-- z s3s2s1s0
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
z3 <= (not s (3) and not s (2) and not s (1) and not s (0));
z4 <= (not s (3) and not s (2) and not s (1) and s (0));
z1 <= (not s (3) and not s (2) and s (1) and not s (0));
z7 <= (not s (3) and not s (2) and s (1) and s (0));
z12 <= (not s (3) and s (2) and not s (1) and not s (0));
z6 <= (not s (3) and s (2) and not s (1) and s (0));
z2 <= (not s (3) and s (2) and s (1) and not s (0));
z8 <= (not s (3) and s (2) and s (1) and s (0));
z9 <= (s (3) and not s (2) and not s (1) and not s (0));
z10 <= (s (3) and not s (2) and not s (1) and s (0));
z11 <= (s (3) and not s (2) and s (1) and not s (0));
z5 <= (s (3) and s (2) and s (1) and s (0));
sadd <= '0';
c <= d;
nul <= d (31);
testnull: FOR i IN 30 DOWNTO 0 GENERATE
nul <= d (i) nor nul;
END GENERATE;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (3 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
begin
-- 00 add
-- 01 sub
-- 10 nutze das func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
-- x1 : add
-- x2 : sub
-- x3 : and
-- x4 : or
-- x5 : nor
-- x6 : slt
-- x7 : xor
-- x8 : sll
-- x9 : srl
-- x10: sra
-- x11: mult
-- x12: div
-- aluop: 10 ...
-- ... func:
-- 100 000 - add 4 0
-- 100 010 - sub 4 2
-- 100 100 - and 4 4
-- 100 101 - or 4 5
-- 100 111 - nor 4 7
-- 101 010 - slt 5 2
-- 100 110 - xor 4 6
-- 000 000 - sll 0 0
-- 000 011 - sra 0 3
-- 000 010 - srl 0 2
-- 011 000 - mult 3 0
-- 011 010 - div 3 2
x1 <= (not aluop (1) and not aluop (0)) or
(aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
x2 <= (not aluop (1) and aluop (0)) or
(aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
x3 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
x4 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
x5 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
x6 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
x7 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
x8 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
x9 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
x10 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
x11 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
x12 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- vier bit
-- 0010 - add
-- 0110 - sub
-- 0000 - and
-- 0001 - or
-- 1111 - slt
-- selber erweitert:
-- x
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity or32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of or32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) or a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity nor32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of nor32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) nor a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity xor32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of xor32 is
begin
genor32: FOR i IN 31 DOWNTO 0 GENERATE
c (i) <= b (i) xor a (i);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sll32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of sll32 is
begin
genor32: FOR i IN 30 DOWNTO 0 GENERATE
c (i) <= a (i+1);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity srl32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of srl32 is
begin
genor32: FOR i IN 31 DOWNTO 1 GENERATE
c (i) <= a (i-1);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity slt32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of slt32 is
-- not implemented yet
begin
genor32: FOR i IN 31 DOWNTO 1 GENERATE
c (i) <= a (i-1);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity sra32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of sra32 is
-- not implemented yet
begin
genor32: FOR i IN 31 DOWNTO 1 GENERATE
c (i) <= a (i-1);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity mult32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of mult32 is
-- not implemented yet, comes soon
begin
genor32: FOR i IN 31 DOWNTO 1 GENERATE
c (i) <= a (i-1);
END GENERATE;
end;
library ieee;
use ieee.std_logic_1164.all;
entity div32 is
port (
a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (31 downto 0);
c: out std_logic_vector (31 downto 0)
);
end;
architecture behaviour of div32 is
-- not implemented yet
begin
genor32: FOR i IN 31 DOWNTO 1 GENERATE
c (i) <= a (i-1);
END GENERATE;
end;
|
kleiner nachtrag - das funcfeld und die operation - add und sub - 00 und 01 sind es nicht wegen dem rudimentaeren, sondern sie sind es, wegen addi und subi, was ein anderes verhalten beim befehlsdekodierer ausloest, bei allen klassischen arith/logic Befehlen wird das func feld genutzt, und op ist immer 000 000, sie werden das gleich in der implementation sehen es geht deswegen nicht, weil - das Befehlsdekoder sich bei addi anders verhaelt ich mache die cpu jetzt so, dass sie nicht alle befehle gleich implementiert, dabei wird sie andi erst mal nicht koennen, nicht sofort, was einfach waere, aber laden und speichern und verzweigungen wenigstens teilweise kann, verzweigung das befehlsdekoder kommt gleich. Es liegt in der natur der Sache, dass die CPU bisher all das kann, wenn es das Befehlsdekoder kann
library ieee;
use ieee.std_logic_1164.all;
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
signal x2: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
x2 <= not opcode (5) and not opcode (4) and not opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
-- gehoert in funktionsdekodierer
-- x2, 1 alle opcode 0
-- opcode, func feld
-- 00 000, 100 000 - add
-- 00 100, xxx xxx - addi
-- 00 000, 100 100 - and
-- 00 000, 100 111 - nor
-- 00 000, 100 101 - or
-- 00 000, 101 010 - slt
-- 00 000, 101 011 - sub
-- 00 000, 100 110 - xor
-- 00 000, 000 000 - sll
-- 00 000, 000 010 - srl
-- 00 000, 000 011 - sra
-- 00 000, 011 010 - div
-- 00 000, 011 000 - mult
-- gehoert in funktionsdekodierer
-- y1 <= func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- add
-- y2 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0); -- and
-- y3 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0); -- nor
-- y4 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0); -- or
-- y5 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slt
-- y6 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sub
-- y7 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0); -- xor
-- y8 <= not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- sll
-- y9 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slr
-- y10 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sra
-- y11 <= not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0); -- div
-- y12 <= not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0); -- mult
memtoreg <= x0;
memwrite <= x0;
branch <= x0;
alusrc <= x0 or x1;
regdst <= x0 or not x1; ---? Bei immidiate - 15:15 - ist aber x1
regwrite <= x0 or x1 or x2;
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
-- aluop x
-- 0 0 - (0)
-- 0 1 1
-- 1 0 2
-- x x -
aluop (1) <= x0 or x1;
aluop (0) <= x0 or x2;
end;
library ieee;
use ieee.std_logic_1164.all;
entity funcdecode is
port (
aluop: in std_logic_vector (1 downto 0);
func: in std_logic_vector (5 downto 0);
aluoperation: out std_logic_vector (3 downto 0)
);
end;
architecture behaviour of funcdecode is
signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
begin
-- 00 add
-- 01 sub
-- 10 nutze das func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- add
x0 <= '0';
-- x1 : add
-- x2 : sub
-- x3 : and
-- x4 : or
-- x5 : nor
-- x6 : slt
-- x7 : xor
-- x8 : sll
-- x9 : srl
-- x10: sra
-- x11: mult
-- x12: div
-- aluop: 10 ...
-- ... func:
-- 100 000 - add 4 0
-- 100 010 - sub 4 2
-- 100 100 - and 4 4
-- 100 101 - or 4 5
-- 100 111 - nor 4 7
-- 101 010 - slt 5 2
-- 100 110 - xor 4 6
-- 000 000 - sll 0 0
-- 000 011 - sra 0 3
-- 000 010 - srl 0 2
-- 011 000 - mult 3 0
-- 011 010 - div 3 2
x1 <= (not aluop (1) and not aluop (0)) or
(aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
x2 <= (not aluop (1) and aluop (0)) or
(aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
x3 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
x4 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
x5 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
x6 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
x7 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
x8 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
x9 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
x10 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
x11 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
x12 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div
-- x2, 1 alle opcode 0
-- opcode, func feld
-- 00 000, 100 000 - add
-- 00 100, xxx xxx - addi
-- 00 000, 100 100 - and
-- 00 000, 100 111 - nor
-- 00 000, 100 101 - or
-- 00 000, 101 010 - slt
-- 00 000, 101 011 - sub
-- 00 000, 100 110 - xor
-- 00 000, 000 000 - sll
-- 00 000, 000 010 - srl
-- 00 000, 000 011 - sra
-- 00 000, 011 010 - div
-- 00 000, 011 000 - mult
-- gehoert in funktionsdekodierer
-- y1 <= func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- add
-- y2 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0); -- and
-- y3 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0); -- nor
-- y4 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0); -- or
-- y5 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slt
-- y6 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sub
-- y7 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0); -- xor
-- y8 <= not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- sll
-- y9 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slr
-- y10 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sra
-- y11 <= not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0); -- div
-- y12 <= not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0); -- mult
-- also
-- a1 a0 ao2 ao1 ao0
-- 0 0 0 1 0
-- 0 1 1 1 0
-- ... func feld
-- 010 - add
-- 110 - sub
-- 000 - and
-- 001 - or
-- 111 - slt
-- vier bit
-- 0010 - add
-- 0110 - sub
-- 0000 - and
-- 0001 - or
-- 1111 - slt
-- selber erweitert:
-- x
-- 3 0 0 0 0 and
-- 4 0 0 0 1 or
-- 1 0 0 1 0 add
-- 7 0 0 1 1 xor
-- 12 0 1 0 0 div
-- 6 0 1 0 1 nor
-- 2 0 1 1 0 sub
-- 8 0 1 1 1 sll
-- 9 1 0 0 0 sra
-- 10 1 0 0 1 srl
-- 11 1 0 1 0 mult
-- 5 1 1 1 1 slt
aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;
end;
|
-- mit store - word - kurze pause
entity opdecode is
port (
opcode: in std_logic_vector (5 downto 0);
memtoreg: out std_logic;
memwrite: out std_logic;
branch: out std_logic;
alusrc: out std_logic;
regdst: out std_logic;
regwrite: out std_logic;
aluop: out std_logic_vector (1 downto 0)
);
end;
architecture behaviour of opdecode is
signal x0: std_logic;
signal x1: std_logic;
signal x2: std_logic;
begin
-- addi
-- 001000 rs rt imm
-- op5 op4 op3 op2 op1 op0
-- 0 0 1 0 0 0
-- x0: nothing
-- x1: addi
-- x0 <= '0'
-- x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
-- memtoreg <= x0 or ...;
-- memwrite <= x0 or ...;
-- branch <= x0 or ...;
-- ...
-- (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate
x0 <= '0';
x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
-- gehoert in funktionsdekodierer
-- x2, 1 alle opcode 0
-- opcode, func feld
-- 00 000, 100 000 - add
-- 00 100, xxx xxx - addi
-- 00 000, 100 100 - and
-- 00 000, 100 111 - nor
-- 00 000, 100 101 - or
-- 00 000, 101 010 - slt
-- 00 000, 101 011 - sub
-- 00 000, 100 110 - xor
-- 00 000, 000 000 - sll
-- 00 000, 000 010 - srl
-- 00 000, 000 011 - sra
-- 00 000, 011 010 - div
-- 00 000, 011 000 - mult
-- gehoert in funktionsdekodierer
-- y1 <= func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- add
-- y2 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0); -- and
-- y3 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0); -- nor
-- y4 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0); -- or
-- y5 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slt
-- y6 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sub
-- y7 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0); -- xor
-- y8 <= not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- sll
-- y9 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slr
-- y10 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sra
-- y11 <= not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0); -- div
-- y12 <= not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0); -- mult
memtoreg <= x0 and (not x1 or not x2);
memwrite <= x0 and (not x1 or x2);
branch <= x0 and (not x1 or not x2);
alusrc <= x0 or (not x1 or x2); -- weil 0 +4
regdst <= x0 or (not x1 or x2); ---? Bei immidiate - 15:15 - ist aber x1
regwrite <= x0 or (x1 or not x2);
-- LOAD WORD
-- STORE WORD
-- MUX 1 - HIGH - ALUSrc
-- MUX 2 - MemToReg - LOW
-- WE - Datenspeicher - MemWrite - HIGH
-- WE - Registersatz - Regwrite - LOW
-- MUX 3 - Achtung - LOW - 20:16 von oben her gesehen, also LOw
-- MUX 4 - Branch LOW
x2 <= opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
-- aluop
-- 00 -- add
-- 01 -- sub
-- 10 -- nutze das func feld
-- 11
-- aluop x
-- 0 0 - (0)
-- 0 1 1
-- 1 0 2
-- x x -
aluop (1) <= x0 or x1;
aluop (0) <= x0 or x2;
end;
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