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ARM - Cortex M7
ADC
ADD
AND
B
BIC
BL
BX
CDP
CMN
CMP
EOR
LDC
LDM
LDR
MCR
MLA
MOV
MRC
MRS
MUL
MVN
ORR
RSB
RSC
SBC
STC
STM
STR
SUB
SWI
SWP
TEQ
TST
ADC Add with Carry
ADD Add
AND AND
B Branch
BIC Bit Clear
BL Branch with Link
BX Branch and Exchange
CDP Copressor Data Processing
CMN Compare Negative
CMP Compare
EOR Exclusive OR
LDC Load Coprocessor from memory
LDM Load Multiple Registers
LDR Load Register from memory
MCR Move CPU Register to copressor register
MLA Multiply Accumulate
MOV Move Register or Constant
MRC Move from copressor to CPU Register
MRS Move PSR status/flags to registers
MUL Multiply
MVN Move negative register
ORR OR
RSB Reverse Subtract
RSC Reverse Subtract with Carry
SBC Subtract with Carry
STC Store Copressor register to memory
STM Store Multiply
STR Store Registers to memory
SUB Subtract
SWI Software Interrupt
SWP Swap registers with memory
TEQ Test bitwise equality
TST Test bits
Suffix
EQ
NE
CS
CC
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
0000 EQ
0001 NE
0010 CS
0011 CC
0100 MI
0101 PL
0110 VS
0111 VC
1000 HI
1001 LS
1010 GE
1011 LT
1100 GT
1101 LE
1110 AL
Register: R0 bis R12
R0
R1
R2
R3
R4
...
R12
SP (R13)
LR (R14)
PC (R15)
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
1.) LOW Registers
2.) HIGH Registers
1.) LOW Registers: R0 .. R7
2.) HIGH Registers: R8 .. R15
1.) LOW Registers: R0 .. R7
2.) HIGH Registers: R8 .. R15, R8 .. R12, SP (R13), LC (R14), PC (R15)
1.) General Purpose Registers
2.) Stack Pointer
3.) Link Register
4.) Program Counter
5.) Special Registers
1.) PSR Program Status Register
2.) Exception mask register
1.) PRIMASK
2.) FAULTMASK
3.) BASEPRI
3.) CONTROL Registers
PSR Program Status Register
Exception mask register
CONTROL Registers
13 general-purpose registers, R0-R12.
Stack Pointer (SP), R13 alias of banked registers, SP_process and SP_main.
Link Register (LR), R14.
Program Counter (PC), R15.
Special-purpose Program Status Registers (xPSR).
registers that control the operation of the processor
System Control Space.
Access Control Space.
Identification Space.
Cache Maintenance Space.
Auxiliary Control Register.
CPUID Base Register.
Cache Level ID Register.
Cache Size ID Register.
Cache Size Selection Register.
Instruction and Data Tightly-Coupled Memory Control Registers.
AHBP Control Register.
Cache Control Register.
Auxiliary Bus Fault Status Register.
Instruction Error bank Register 0-1.
Data Error bank Register 0-1.
AHB Slave Control Register.
the system control registers
0xE000E008
0xE000E00C
0xE000E010
0xE000E014
0xE000E018
0xE000E01C
0xE000ED00
0xE000ED04
0xE000ED08
0xE000ED0C
0xE000ED10
0xE000ED14
0xE000ED18
0xE000ED1C
0xE000ED20
0xE000ED24
0xE000ED28
0xE000ED2C
0xE000ED30
0xE000ED34
0xE000ED38
0xE000ED40
0xE000ED44
0xE000ED48
0xE000ED4C
0xE000ED50
0xE000ED54
0xE000ED58
0xE000ED5C
0xE000ED60
0xE000ED64
0xE000ED68
0xE000ED6C
0xE000ED70
0xE000ED78
0xE000ED7C
0xE000ED80
0xE000ED84
0xE000ED88
0xE000EF00
0xE000EF50
0xE000EF54
0xE000EF58
0xE000EF5C
0xE000EF60
0xE000EF64
0xE000EF68
0xE000EF6C
0xE000EF70
0xE000EF74
0xE000EF78
0xE000EF7C
0xE000EF80
0xE000EF90
0xE000EF94
0xE000EF98
0xE000EF9C
0xE000EFA0
0xE000EFA4
0xE000EFA8
0xE000EFB0
0xE000EFB4
0xE000EFBC
0xE000EFD0
0xE000EFD4
0xE000EFD8
0xE000EFDC
0xE000EFE0
0xE000EFE4
0xE000EFE8
0xE000EFEC
0xE000EFF0
0xE000EFF4
0xE000EFF8
0xE000EFFC
0xE000E008 ACTLR
0xE000E00C
0xE000E010 SYST_CSR
0xE000E014 SYST_RVR
0xE000E018 SYST_CVR
0xE000E01C SYST_CALIB
0xE000ED00 CPUID
0xE000ED04 ICSR
0xE000ED08 VTOR
0xE000ED0C AIRCR
0xE000ED10 SCR
0xE000ED14 CCR
0xE000ED18 SHPR1
0xE000ED1C SHPR2
0xE000ED20 SHPR3
0xE000ED24 SHCSR
0xE000ED28 CFSR
0xE000ED2C HFSR
0xE000ED30 DFSR
0xE000ED34 MMFAR
0xE000ED38 BFAR
0xE000ED40 ID_PFR0
0xE000ED44 ID_PFR1
0xE000ED48 ID_DFR0
0xE000ED4C ID_AFR0
0xE000ED50 ID_MMFR0
0xE000ED54 ID_MMFR1
0xE000ED58 ID_MMFR2
0xE000ED5C ID_MMFR3
0xE000ED60 ID_ISAR0
0xE000ED64 ID_ISAR1
0xE000ED68 ID_ISAR2
0xE000ED6C ID_ISAR3
0xE000ED70 ID_ISAR4
0xE000ED78 CLIDR
0xE000ED7C CTR
0xE000ED80 CCSIDR
0xE000ED84 CSSELR
0xE000ED88 CPACR
0xE000EF00 STIR
0xE000EF50 ICIALLU
0xE000EF54
0xE000EF58 ICIMVAU
0xE000EF5C DCIMVAC
0xE000EF60 DCISW
0xE000EF64 DCCMVAU
0xE000EF68 DCCMVAC
0xE000EF6C DCCSW
0xE000EF70 DCCIMVAC
0xE000EF74 DCCISW
0xE000EF78 BPIALL
0xE000EF7C
0xE000EF80
0xE000EF90 CM7_ITCMCR
0xE000EF94 CM7_DTCMCR
0xE000EF98 CM7_AHBPCR
0xE000EF9C CM7_CACR
0xE000EFA0 CM7_AHBSCR
0xE000EFA4
0xE000EFA8 CM7_ABFSR
0xE000EFB0 IEBR0
0xE000EFB4 IEBR1
0xE000EFB8 DEBR0
0xE000EFBC DEBR1
0xE000EFD0 PID4
0xE000EFD4 PID5
0xE000EFD8 PID6
0xE000EFDC PID7
0xE000EFE0 PID0
0xE000EFE4 PID1
0xE000EFE8 PID2
0xE000EFEC PID3
0xE000EFF0 CID0
0xE000EFF4 CID1
0xE000EFF8 CID2
0xE000EFFC CID3
0xE000E008 ACTLR Auxiliary Control Register
0xE000E00C Reserved
0xE000E010 SYST_CSR SysTick Control and Status Register
0xE000E014 SYST_RVR SysTick Reload Value Register
0xE000E018 SYST_CVR SysTick Current Value Register
0xE000E01C SYST_CALIB SysTick Calibration Value Register
0xE000ED00 CPUID CPUID Base Register
0xE000ED04 ICSR Interrupt Control and State Register
0xE000ED08 VTOR Vector Table Offset Register
0xE000ED0C AIRCR Application Interrupt and Reset Control Register
0xE000ED10 SCR System Control Register
0xE000ED14 CCR Configuration and Control Register
0xE000ED18 SHPR1 System Handler Priority Register 1
0xE000ED1C SHPR2 System Handler Priority Register 2
0xE000ED20 SHPR3 System Handler Priority Register 3
0xE000ED24 SHCSR System Handler Control and State Register
0xE000ED28 CFSR Configurable Fault Status Registers[e]
0xE000ED2C HFSR HardFault Status Register
0xE000ED30 DFSR Debug Fault Status Register
0xE000ED34 MMFAR MemManage Fault Address Register[f]
0xE000ED38 BFAR BusFault Address Register[f]
0xE000ED40 ID_PFR0 Processor Feature Register 0
0xE000ED44 ID_PFR1 Processor Feature Register 1
0xE000ED48 ID_DFR0 Debug Feature Register 0[g]
0xE000ED4C ID_AFR0 Auxiliary Feature Register 0
0xE000ED50 ID_MMFR0 Memory Model Feature Register 0
0xE000ED54 ID_MMFR1 Memory Model Feature Register 1
0xE000ED58 ID_MMFR2 Memory Model Feature Register 2
0xE000ED5C ID_MMFR3 Memory Model Feature Register 3
0xE000ED60 ID_ISAR0 Instruction Set Attributes Register 0
0xE000ED64 ID_ISAR1 Instruction Set Attributes Register 1
0xE000ED68 ID_ISAR2 Instruction Set Attributes Register 2
0xE000ED6C ID_ISAR3 Instruction Set Attributes Register 3
0xE000ED70 ID_ISAR4 Instruction Set Attributes Register 4
0xE000ED78 CLIDR Cache Level ID Register
0xE000ED7C CTR Cache Type Register
0xE000ED80 CCSIDR Cache Size ID Register
0xE000ED84 CSSELR Cache Size Selection Register
0xE000ED88 CPACR Coprocessor Access Control Register
0xE000EF00 STIR Software Triggered Interrupt Register
0xE000EF50 ICIALLU Instruction cache invalidate all to Point of Unification (PoU)
0xE000EF54 Reserved
0xE000EF58 ICIMVAU Instruction cache invalidate by address to PoU
0xE000EF5C DCIMVAC Data cache invalidate by address to Point of Coherency (PoC)
0xE000EF60 DCISW Data cache invalidate by set/way
0xE000EF64 DCCMVAU Data cache by address to PoU
0xE000EF68 DCCMVAC Data cache clean by address to PoC
0xE000EF6C DCCSW Data cache clean by set/way
0xE000EF70 DCCIMVAC Data cache clean and invalidate by address to PoC
0xE000EF74 DCCISW Data cache clean and invalidate by set/way
0xE000EF78 BPIALL Not implemented
0xE000EF7C Reserved
0xE000EF80 Reserved
0xE000EF90 CM7_ITCMCR Instruction and Data Tightly-Coupled Memory Control Registers
0xE000EF94 CM7_DTCMCR Instruction and Data Tightly-Coupled Memory Control Registers
0xE000EF98 CM7_AHBPCR AHBP Control Register
0xE000EF9C CM7_CACR Cache Control Register
0xE000EFA0 CM7_AHBSCR AHB Slave Control Register
0xE000EFA4 Reserved
0xE000EFA8 CM7_ABFSR Auxiliary Bus Fault Status Register
0xE000EFB0 IEBR0 Instruction Error bank Register 0-1
0xE000EFB4 IEBR1 Instruction Error bank Register 0-1
0xE000EFB8 DEBR0 Data Error bank Register 0-1
0xE000EFBC DEBR1 Data Error bank Register 0-1
See the Component and Peripheral ID register formats in the Armv7-M Architecture Reference Manual.
0xE000EFD0 PID4
0xE000EFD4 PID5
0xE000EFD8 PID6
0xE000EFDC PID7
0xE000EFE0 PID0
0xE000EFE4 PID1
0xE000EFE8 PID2
0xE000EFEC PID3
0xE000EFF0 CID0
0xE000EFF4 CID1
0xE000EFF8 CID2
0xE000EFFC CID3
Auxiliary Control Register.
CPUID Base Register.
Cache Level ID Register.
Cache Size ID Register.
Cache Size Selection Register.
Instruction and Data Tightly-Coupled Memory Control Registers.
AHBP Control Register.
Cache Control Register.
Auxiliary Bus Fault Status Register.
Instruction Error bank Register 0-1.
Data Error bank Register 0-1.
AHB Slave Control Register.
GPIO Registers
one processor register must be a pointer to the I/O register
another register will contain the value to be written
an indexed write instruction performs the operation
MODER
OTYPER
OSPEEDR
PUPDR
IDR
ODR
BSRR
LCKR
MODER: Mode Register, Die Funktion des Pins einstellen,
00: Input (Reset Status)
01: GPIO (ODR-Ausgabe)
10: Alternative Funktion
11: Analog Modus
OTYPER
0: Output push-pull
1: Output open-drain
OSPEEDR
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
PUPDR
00: No PullUp, PullDown
01: PullUp
10: PullDown
11: Reserviert
IDR
ODR
BSRR
0..15 Setzen (hat Priorit"at)
16..31 R"ucksetzen
LCKR